Stabilization of resistive memory

Patent metadata

Field	Value
Publication number	US-9224471-B2
Application number	US-201514593234-A
Country	US
Kind code	B2
Filing date	Jan 9, 2015
Priority date	Oct 18, 2011
Publication date	Dec 29, 2015
Grant date	Dec 29, 2015

Abstract

The present disclosure includes apparatuses and methods including stabilization of resistive memory. A number of embodiments include applying a programming signal to a resistive memory cell, wherein the programming signal includes a first portion having a first polarity and a second portion having a second polarity, wherein the second polarity is opposite the first polarity.

First claim

What is claimed is:

1. A method of operating a resistive memory cell, comprising:
applying a programming signal to a resistive memory cell, wherein the programming signal includes:
a programming pulse; and
a stabilization pulse.

2. The method of claim 1 , wherein the programming pulse and the stabilization pulse have opposite polarities.

3. The method of claim 1 , wherein the programming signal includes a program verify pulse.

4. The method of claim 1 , wherein the programming signal includes an additional programming pulse.

5. The method of claim 4 , wherein the stabilization pulse is between the programming pulse and the additional programming pulse.

6. The method of claim 4 , wherein the stabilization pulse is after the programming pulse and the additional programming pulse.

7. The method of claim 1 , wherein the programming pulse has a shorter duration than the stabilization pulse.

8. The method of claim 1 , wherein the programming pulse has a greater amplitude than the stabilization pulse.

9. An apparatus, comprising:
an array of resistive memory cells; and
a controller coupled to the array and configured to apply a programming signal to a selected cell of the array, wherein the programming signal includes:
a programming pulse; and
a stabilization pulse after the programming pulse.

10. The apparatus of claim 9 , wherein:
the programming pulse has a positive polarity; and
the stabilization pulse has a negative polarity.

11. The apparatus of claim 9 , wherein:
the programming pulse has a negative polarity; and
the stabilization pulse has a positive polarity.

12. The apparatus of claim 9 , wherein the stabilization pulse is immediately after the programming pulse.

13. The apparatus of claim 9 , wherein the programming signal includes a program verify pulse after the programming pulse.

14. The apparatus of claim 13 , wherein the stabilization pulse is after the program verify pulse.

15. The apparatus of claim 9 , wherein the array of resistive memory cells is an array of resistive random access memory (RRAM) cells.

16. A method of operating a resistive memory cell, comprising:
applying a programming pulse to a resistive memory cell; and
applying a stabilization pulse to the resistive memory cell;
wherein the programming pulse and the stabilization pulse have opposite polarities.

17. The method of claim 16 , wherein applying the programming pulse to the resistive memory cell programs the cell to a resistance state corresponding to a target data state.

18. The method of claim 17 , wherein applying the stabilization pulse to the resistive memory cell stabilizes the programmed resistance state of the cell.

19. The method of claim 17 , wherein applying the stabilization pulse to the resistive memory cell prevents the target data state of the cell from changing during subsequent operation of the cell.

20. The method of claim 16 , wherein applying the stabilization pulse to the resistive memory cell prevents formation of weak conductive filaments in the cell during subsequent operation of the cell.

Assignees

• Micron Technology Inc

Inventors

• Chen Xiaonan

Classifications

• G11C11/5685

  using storage elements comprising metal oxide memory material, e.g. perovskites · CPC title

• G11C13/0004

  comprising amorphous/crystalline phase transition cells · CPC title

• G11C11/5678

  using amorphous/crystalline phase transition storage elements · CPC title

• G11C13/0007

  comprising metal oxide memory material, e.g. perovskites · CPC title

• G11C11/1675

  Writing or programming circuits or methods · CPC title