Supply margining method and apparatus

Patent metadata

Field	Value
Publication number	US-9223367-B2
Application number	US-201314090519-A
Country	US
Kind code	B2
Filing date	Nov 26, 2013
Priority date	Mar 31, 2008
Publication date	Dec 29, 2015
Grant date	Dec 29, 2015

Abstract

In accordance with some embodiments, margining routines to determine acceptable voltage command values for specific CPU implementations at one or more different operating levels may be provided.

First claim

What is claimed is:

1. An apparatus, comprising:
a voltage regulator operable with first voltage guardband values associated with upper and lower limits of a voltage command value; and
a processor to be coupled to the voltage regulator to provide it with a voltage command and to receive a supply voltage corresponding to the commanded voltage and to receive operating parameter information from the voltage regulator, the processor to determine allowable voltage command values for later operation based on operating parameters from the voltage regulator,
wherein the processor is operable to determine second voltage guardband values associated with upper and lower limits of the allowable voltage command values,
wherein the second voltage guardband values are determined based on a difference between the received supply voltage and a requested supply voltage, and
wherein the first voltage guardband values are higher than the second voltage guardband values.

2. The apparatus of claim 1 , wherein the voltage regulator is an integrated voltage regulator with a semiconductor die, switching elements, and magnetic components integrated into a common package.

3. The apparatus of claim 1 , wherein the voltage regulator when operated is switched in excess of 10 MHz.

4. The apparatus of claim 1 , wherein the operating parameter information includes regulator information with responsiveness of at least 200 nano-seconds.

5. The apparatus of claim 1 , wherein the processor is controlled by an external controller to determine the allowable voltage command values.

6. The apparatus of claim 1 , wherein the voltage regulator and processor are part of a common package.

7. An apparatus, comprising:
a computer having a processor and a voltage regulator to provide the processor with a regulated received voltage in response to a voltage command for a commanded voltage, wherein the regulated received voltage has a voltage level which is less than a voltage level of the commanded voltage during processor operation;
logic for determining voltage command guardband information corresponding to one or more differences between values of the received voltage and commanded voltage under different test conditions; and
a memory for storing the voltage command information and the determined voltage command guardband information for later use by the processor.

8. The apparatus of claim 7 , wherein the voltage command guardband information comprises guardband values determined for separate commanded voltages at different processor performance levels.

9. The apparatus of claim 7 , wherein the guardband information comprises voltage command values.

10. The apparatus of claim 7 , wherein the processor comprising logic for receiving operating parameter information from the voltage regulator and for determining voltage command guardband information based on said operating parameter information.

11. A system comprising:
a memory;
a voltage regulator operable with first voltage guardband values associated with upper and lower limits of a voltage command value;
a processor coupled to the memory, the processor to be coupled to the voltage regulator to provide it with a voltage command and to receive a supply voltage corresponding to the commanded voltage and to receive operating parameter information from the voltage regulator, the processor to determine allowable voltage command values for later operation based on the operating parameters from the voltage regulator,
wherein the processor is operable to determine second voltage guardband values associated with upper and lower limits of the allowable voltage command values and
wherein the second voltage guardband values are determined based on a difference between the received supply voltage and a requested supply voltage, and
wherein the second voltage guardband values are lower than the first voltage guardband values; and

a wireless interface for allowing the processor to communicate with another device.

12. The system of claim 11 , wherein the voltage regulator is an integrated voltage regulator with a semiconductor die, and wherein switching elements and magnetic components associated with the voltage regulator are integrated into a common package.

13. The system of claim 11 , wherein the voltage regulator when operated is switched in excess of 10 MHz.

14. The system of claim 11 , wherein the operating parameter information includes regulator information with responsiveness of at least 200 ns.

15. The system of claim 11 , wherein the processor is controlled by an external controller to determine the allowable voltage command values.

16. The system of claim 11 , wherein the voltage regulator and processor are part of a common package.

17. The apparatus of claim 1 , wherein the voltage regulator to dynamically adjust load-line of the processor to save power during normal operation.

18. The apparatus of claim 1 , wherein the voltage regulator comprises at least two voltage regulator domains to provide at least two voltage supplies to the processor.

19. The apparatus of claim 18 , wherein the processor comprises at least two processor cores to receive the at least two voltage supplies, respectively.

20. The apparatus of claim 1 , wherein the processor includes a storage medium for saving the second guardband values and associated performance level of the processor.

Assignees

• Intel Corp

Inventors

• Lam Son H
• Koertzen Henry W
• Dibene Ii Joseph T
• Patzer Steven D

Classifications

• G06F1/26 Primary

  Power supply means, e.g. regulation thereof (for memories G11C) · CPC title

• G05F1/66

  Regulating electric power · CPC title

• G06F1/3243

  Power saving in microcontroller unit · CPC title

• G06F1/3203 Primary

  Power management, i.e. event-based initiation of a power-saving mode · CPC title

• G06F1/266 Primary

  Arrangements to supply power to external peripherals either directly from the computer or under computer control, e.g. supply of power through the communication port, computer controlled power-strips · CPC title