Multi-threshold voltage devices and associated techniques and configurations

Patent metadata

Field	Value
Publication number	US-9219155-B2
Application number	US-201314108265-A
Country	US
Kind code	B2
Filing date	Dec 16, 2013
Priority date	Dec 16, 2013
Publication date	Dec 22, 2015
Grant date	Dec 22, 2015

Abstract

Embodiments of the present disclosure describe multi-threshold voltage devices and associated techniques and configurations. In one embodiment, an apparatus includes a semiconductor substrate, a channel body disposed on the semiconductor substrate, a first gate electrode having a first thickness coupled with the channel body and a second gate electrode having a second thickness coupled with the channel body, wherein the first thickness is greater than the second thickness. Other embodiments may be described and/or claimed.

First claim

What is claimed is:

1. An apparatus comprising:
a semiconductor substrate;
a channel body disposed on the semiconductor substrate;
a first gate electrode having a first thickness coupled with the channel body; and
a second gate electrode having a second thickness coupled with the channel body, wherein the first thickness is greater than the second thickness, and wherein the first gate electrode and the second gate electrode are composed of a first material having a same chemical composition; and
a third gate electrode having a third thickness coupled with the channel body, wherein the third thickness is greater than the first thickness and the third gate electrode is composed of a second material having a different chemical composition than the first material.

2. The apparatus of claim 1 , further comprising:
a fourth gate electrode having a fourth thickness coupled with the channel body, wherein the second thickness is greater than the fourth thickness and wherein the fourth gate electrode is composed of the first material.

3. The apparatus of claim 2 , wherein:
the second gate electrode is disposed between the first gate electrode and the fourth gate electrode; and
the fourth gate electrode is disposed between the second gate electrode and the third gate electrode.

4. The apparatus of claim 1 , wherein:
the first material is a p-type workfunction metal; and
the second material is an n-type workfunction metal.

5. The apparatus of claim 1 , wherein the first material has an n-type or p-type composition, the apparatus further comprising:
the second material disposed on the first material of the first gate electrode and the second gate electrode, wherein the second material has n-type composition if the first material has p-type composition and has p-type composition if the first material has n-type composition.

6. The apparatus of claim 1 , wherein the first material has an n-type or p-type composition, the apparatus further comprising:
the second material disposed on the first material of the first gate electrode; and
a third material disposed on the first material of the second gate electrode, wherein the second material has n-type composition if the first material has p-type composition and has p-type composition if the first material has n-type composition, and wherein the second material and the third material have a different chemical composition.

7. The apparatus of claim 1 , wherein the first material has an n-type or p-type composition, the apparatus further comprising:
the second material disposed on the first material of the first gate electrode; and
a third material disposed on the second material, wherein the third material is a fill material that is more p-type than the first material and more n-type than the second material.

8. The apparatus of claim 1 , further comprising:
a gate dielectric film disposed between the first gate electrode and the channel body and between the second gate electrode and the channel body.

9. The apparatus of claim 1 , wherein the channel body is a fin structure composed of a semiconductor material that is undoped.

10. The apparatus of claim 1 , wherein the first thickness is equal to 30 Angstroms or less.

11. A method comprising:
providing a channel body disposed on a semiconductor substrate; and
forming a first gate electrode and a second gate electrode coupled with the channel body, wherein the first gate electrode has a first thickness, the second gate electrode has a second thickness and the first thickness is greater than the second thickness, wherein forming the first gate electrode and the second gate electrode comprises:
simultaneously depositing an electrode material in a first region of the first gate electrode and a second region of the second gate electrode as part of a first deposition;
selectively removing the electrode material in the second region as part of a first removal; and
simultaneously depositing the electrode material in the first region and the second region as part of a second deposition subsequent to selectively removing the electrode material in the second region; and

forming a third gate electrode coupled with the channel body, wherein the third gate electrode has a third thickness and the second thickness is greater than the third thickness, wherein forming the third gate electrode comprises:
simultaneously depositing the electrode material in a third region of the third gate electrode when simultaneously depositing the electrode material in the first region and the second region as part of the first deposition;
selectively removing the electrode material in the third region when selectively removing the electrode material in the second region as part of the first removal;
simultaneously depositing the electrode material in the third region when simultaneously depositing the electrode material in the first region and the second region as part of the second deposition;
selectively removing the electrode material in the third region as part of a second removal; and
simultaneously depositing the electrode material in the first region, the second region and the third region as part of a third deposition subsequent to selectively removing the electrode material in the third region as part of the second removal.

12. The method of claim 11 , wherein the electrode material of the first gate electrode and the second gate electrode have a same n-type or p-type composition, the method further comprising:
depositing another electrode material on the electrode material of the first gate electrode and the second gate electrode, wherein the another electrode material has n-type composition if the electrode material has p-type composition and has p-type composition if the electrode material has n-type composition.

13. The method of claim 11 , wherein forming the first gate electrode comprises replacing a sacrificial material with material of the first gate electrode.

14. The method of claim 11 , further comprising:
forming a fourth gate electrode on the first gate electrode; and
forming a fifth gate electrode on the fourth gate electrode, wherein material of the fifth gate electrode is a fill material that is more p-type than material of the first gate electrode and more n-type than material of the fourth gate electrode.

15. The method of claim 11 , further comprising:
forming a gate dielectric film on the channel body prior to forming the first gate electrode and the second gate electrode.

16. The method of claim 11 , wherein no doping process is performed on the channel body to modulate a threshold voltage of one or more transistors.

17. A method comprising:
providing a channel body disposed on a semiconductor substrate; and
forming a first gate electrode and a second gate electrode coupled with the channel body, wherein the first gate electrode has a first thickness, the second gate electrode has a second thickness and the first thickness is greater than the second thickness, wherein forming the first gate electrode and the second gate electrode comprises:
simultaneously depositing an electrode material in a first region of the first gate electrode and a second region of the second gate electrode as part of a first deposition;
selectively removing the electrode material in the second region; and
simultaneously depositing the electrode material in the first region and the second region as part of a second deposition subsequent to selectively removing the electrode material in the second region; and

forming a third gate electrode having a third thickness coupled

Assignees

• Intel Corp

Inventors

• Steigerwald Joseph M
• Ghani Tahir
• Hu Jenny
• Post Ian R C

Classifications

• H10D64/01324

  characterised by the sectional shape, e.g. T or inverted-T · CPC title

• H10D30/0323

  comprising monocrystalline silicon · CPC title

• H10D30/023

  having multiple independently-addressable gate electrodes influencing the same channel (manufacture or treatment of dual gate TFTs H10D30/031) · CPC title

• H10D64/517

  characterised by the conducting layers · CPC title

• H10D64/518

  characterised by their lengths or sectional shapes · CPC title