High electron mobility transistor and method for forming the same
US-12176414-B2 · Dec 24, 2024 · US
Group III-N transistor on nanoscale template structures
US9219079B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9219079-B2 |
| Application number | US-201414581722-A |
| Country | US |
| Kind code | B2 |
| Filing date | Dec 23, 2014 |
| Priority date | Dec 19, 2012 |
| Publication date | Dec 22, 2015 |
| Grant date | Dec 22, 2015 |
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Abstract
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A III-N semiconductor channel is formed on a III-N transition layer formed on a ( 111 ) or ( 110 ) surface of a silicon template structure, such as a fin sidewall. In embodiments, the silicon fin has a width comparable to the III-N epitaxial film thicknesses for a more compliant seeding layer, permitting lower defect density and/or reduced epitaxial film thickness. In embodiments, a transition layer is GaN and the semiconductor channel comprises Indium (In) to increase a conduction band offset from the silicon fin. In other embodiments, the fin is sacrificial and either removed or oxidized, or otherwise converted into a dielectric structure during transistor fabrication. In certain embodiments employing a sacrificial fin, the III-N transition layer and semiconductor channel is substantially pure GaN, permitting a breakdown voltage higher than would be sustainable in the presence of the silicon fin.
First claim
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What is claimed is: 1. A III-N field effect transistor (FET) disposed on a silicon substrate, the FET comprising: a dielectric anchor disposed over the substrate; a first and second group III-N device layer stack physically separated from each other by the dielectric anchor; and a gate stack disposed over the III-N device layer stacks to control a conductivity of a channel semiconductor layer in each of the III-N device layer stacks. 2. The III-N FET of…
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Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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- What does patent US9219079B2 cover?
- A III-N semiconductor channel is formed on a III-N transition layer formed on a ( 111 ) or ( 110 ) surface of a silicon template structure, such as a fin sidewall. In embodiments, the silicon fin has a width comparable to the III-N epitaxial film thicknesses for a more compliant seeding layer, permitting lower defect density and/or reduced epitaxial film thickness. In embodiments, a transition …
- Who is the assignee on this patent?
- Intel Corp
- What technology area does this patent fall under?
- Primary CPC classification H10D62/8503. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Dec 22 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).