Semiconductor device and method for forming the same
US-2024395669-A1 · Nov 28, 2024 · US
Integrated circuit chips having vertically extended through-substrate vias therein
US9219035B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9219035-B2 |
| Application number | US-201414153478-A |
| Country | US |
| Kind code | B2 |
| Filing date | Jan 13, 2014 |
| Priority date | Jun 10, 2008 |
| Publication date | Dec 22, 2015 |
| Grant date | Dec 22, 2015 |
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Abstract
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Methods of forming an integrated circuit device include forming an interlayer dielectric layer on a first surface of a semiconductor substrate and then forming an interconnect hole that extends through the interlayer dielectric layer and into the semiconductor substrate. A first sidewall spacer layer is formed on a sidewall of the interconnect hole. The semiconductor substrate at a bottom of the interconnect hole is isotropically etched to define an undercut recess in the semiconductor substrate. This etching step is performed using the first sidewall spacer layer as an etching mask. The interconnect hole and the uncut recess are then filled with a through-via electrode. A second surface of the semiconductor substrate is removed for a sufficient duration to expose the uncut recess containing the through-via electrode.
First claim
Opening claim text (preview).
That which is claimed is: 1. An integrated circuit device, comprising: a semiconductor substrate having a plurality of active semiconductor devices therein extending adjacent a first surface thereof and a second surface extending opposite the first surface; an interlayer dielectric layer covering the plurality of active semiconductor devices, on the first surface; a through-via electrode having a main portion being entirely equal in its width and having a bulbous extension be…
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Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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Frequently asked questions
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- What does patent US9219035B2 cover?
- Methods of forming an integrated circuit device include forming an interlayer dielectric layer on a first surface of a semiconductor substrate and then forming an interconnect hole that extends through the interlayer dielectric layer and into the semiconductor substrate. A first sidewall spacer layer is formed on a sidewall of the interconnect hole. The semiconductor substrate at a bottom of th…
- Who is the assignee on this patent?
- Lee Ho-Jin, Lee Kang-Wook, Park Myeong-Soon, and 3 more
- What technology area does this patent fall under?
- Primary CPC classification H10W20/023. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Dec 22 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).