GaN epitaxial growth method

US9218965B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9218965-B2
Application numberUS-201414229285-A
CountryUS
Kind codeB2
Filing dateMar 28, 2014
Priority dateMar 28, 2014
Publication dateDec 22, 2015
Grant dateDec 22, 2015

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Abstract

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By using a nano-scale patterning process, a dislocation defect density of a GaN epitaxy layer can be further reduced. This is because the nano-scale epitaxy structure dimension is advantageous to the reduction of the strain energy accumulated by mismatched lattices, thereby decreasing the possibility of generating defects. It is verified that the nano-scale patterning process can effectively decrease the dislocation defect density of the GaN epitaxial layer on a sapphire substrate. Considering uniformity and reproducibility on the application of the large-size wafer, the invention has utilized the soft mask NIL patterning technology to successfully implement the uniform deposition and position control of the InAs quantum dot on a GaAs substrate. This further utilizes the NIL technology in conjunction with dry-etching to perform the nano-scale patterning on a heterogeneous substrate, such as Si, sapphire or the like.

First claim

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What is claimed is: 1. A gallium nitride epitaxial growth method, comprising the steps of: (1) providing a semiconductor laminated layer or a heterogeneous substrate; (2) forming a platform on the semiconductor laminated layer or the heterogeneous substrate to serve as a use of a flexible nano-imprint; (3) forming a nano-pillar or a nano-hole on the semiconductor laminated layer or the heterogeneous substrate; and (4) forming a heterogeneous epitaxy region on the semiconductor laminated layer or the heterogeneous substrate; wherein the step (3) of forming the nano-pillar or the nano-hole comprises: (i) using the flexible nano-imprint with a predetermined period on the semiconductor laminated layer or the heterogeneous substrate; (ii) performing a dry-etching process once on the semiconductor laminated layer or the heterogeneous substrate to transfer print a nano-pattern; and (iii) performing a peel off process so that the nano-pattern forms the nano-pillar or the nano-hole on the semiconductor laminated layer or the heterogeneous substrate. 2. The method according to claim 1 , wherein the semiconductor laminated layer or the heterogeneous substrate comprises an upper block and a lower block, the lower block is the platform and abuts upon the semiconductor laminated layer or an upper surface of the heterogeneous substrate; and the upper block and the semiconductor laminated layer or the heterogeneous substrate are integrally formed and continuously connected to form a patterned layer of the nano-pillar or the nano-hole. 3. The method according to claim 2 , wherein the upper block is formed by removing the semiconductor laminated layer or the heterogeneous substrate after the flexible nano-imprint is formed on a nano-photoresist layer; and the nano-photoresist layer is oxygen-plasma etched into the nano-pillar or nano-hole. 4. A gallium nitride epitaxial growth method, comprising: providing a substrate; forming a platform on the substrate to serve as a flexible nano-imprint; forming a nano-pillar or hole on the substrate; and forming a heterogeneous epitaxy region on the substrate; wherein the substrate comprises an upper block and a lower block; the lower block abuts upon an upper surface of the substrate, the lower block is the platform of the flexible nano-imprint; and the upper block is integrally formed and is continuously connected to the substrate to form a patterned layer of the nano-pillar or hole. 5. The method according to claim 4 , wherein the substrate is a semiconductor laminated layer or a heterogeneous substrate. 6. The method according to claim 5 , wherein the platform is formed by PECVD or thermal evaporation deposition to obtain a dielectric layer and an oxide layer, then forming the flexible nano-imprint on a nano-photoresist layer, and then using an oxygen plasma to etch the nano-photoresist layer into the nano-pillar or hole. 7. The method according to claim 6 , wherein the upper block is formed by removing the dielectric layer or the oxide layer, and then dry-etching to remove the dielectric layer or the nano-pillar or hole of the oxide layer. 8. The method according to claim 7 , wherein the upper block is to transfer print the nano-pillar or hole on the substrate after dry/wet etching to remove a portion of the substrate. 9. A gallium nitride epitaxial growth method, comprising: providing a semiconductor laminated layer or a heterogeneous substrate; the semiconductor laminated layer or heterogeneous substrate constitute an interface contacting a gallium nitride material; imprinting a flexible nanometer platform on the semiconductor laminated layer or the heterogeneous substrate; and transfer printing a nano-pillar or hole, and using molecule beam epitaxy (MBE) to grow the nano-pillar or hole, formed by transfer printing the gallium nitride material, on the semiconductor laminated layer or the heterogeneous substrate. 10. The method according to claim 9 , wherein a dry/wet etching process is utilized to remove a portion of the semiconductor laminated layer or the heterogeneous substrate to obtain a gallium nitride layer with a depth of about 200 nm on the semiconductor laminated layer or the heterogeneous substrate.

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Classifications

  • characterised by the process involved to create the mask, e.g. lift-off masks or sidewalls or to modify the mask · CPC title

  • Chemical etching · CPC title

  • of Group IV materials · CPC title

  • Lateral overgrowth · CPC title

  • characterised by the preparation of substrate for selective deposition · CPC title

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What does patent US9218965B2 cover?
By using a nano-scale patterning process, a dislocation defect density of a GaN epitaxy layer can be further reduced. This is because the nano-scale epitaxy structure dimension is advantageous to the reduction of the strain energy accumulated by mismatched lattices, thereby decreasing the possibility of generating defects. It is verified that the nano-scale patterning process can effectively de…
Who is the assignee on this patent?
Nat Univ Tsing Hua
What technology area does this patent fall under?
Primary CPC classification H10P14/3416. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Dec 22 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).