Reduced bitcount polygon rasterization

Patent metadata

Field	Value
Publication number	US-9218679-B2
Application number	US-201213647071-A
Country	US
Kind code	B2
Filing date	Oct 8, 2012
Priority date	Oct 8, 2012
Publication date	Dec 22, 2015
Grant date	Dec 22, 2015

Abstract

Techniques are disclosed for carrying out rasterization of a given graphics workload, wherein portions of the workload associated with relatively high bit count operations are processed via a first process path, and portions of the workload associated with relatively lower bit count operations are processed via a second, relatively faster process path, in accordance with an embodiment. In a more general sense, maximal bit count associated with a given primitive can be identified and compared to a threshold to determine which one of multiple available processing paths can be used.

First claim

What is claimed is:

1. A device, comprising:
hardware circuitry comprising a bounding box module configured to calculate a bounding box of a given polygonal primitive describing a three-dimensional scene, the polygon polygonal primitive represented as one or more triangles;
hardware circuitry comprising a translation module configured to translate each triangle from the three-dimensional realm to the two-dimensional realm;
hardware circuitry comprising an edge equations module…

Assignees

• Intel Corp

Inventors

• Subag Jacob
• Benty Nir

Classifications

• G06T2210/12

  Physics · mapped topic

• G06T15/10

  Physics · mapped topic

• G06T11/40 Primary

  Physics · mapped topic