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Parallel hardware and software block processing pipelines

US9215472B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9215472-B2
Application numberUS-201314039729-A
CountryUS
Kind codeB2
Filing dateSep 27, 2013
Priority dateSep 27, 2013
Publication dateDec 15, 2015
Grant dateDec 15, 2015

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A block processing pipeline that includes a software pipeline and a hardware pipeline that run in parallel. The software pipeline runs at least one block ahead of the hardware pipeline. The stages of the pipeline may each include a hardware pipeline component that performs one or more operations on a current block at the stage. At least one stage of the pipeline may also include a software pipeline component that determines a configuration for the hardware component at the stage of the pipeline for processing a next block while the hardware component is processing the current block. The software pipeline component may determine the configuration according to information related to the next block obtained from an upstream stage of the pipeline. The software pipeline component may also obtain and use information related to a block that was previously processed at the stage.

First claim

Opening claim text (preview).

What is claimed is: 1. An apparatus, comprising: a block processing pipeline comprising a plurality of stages, wherein one or more of the plurality of stages of the block processing pipeline each comprises a component of a software pipeline and a component of a hardware pipeline, wherein the software and hardware pipelines are configured to process blocks of pixels from a frame in parallel; wherein the software pipeline component at each of the one or more stages is configured t…

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Frequently asked questions

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What does patent US9215472B2 cover?
A block processing pipeline that includes a software pipeline and a hardware pipeline that run in parallel. The software pipeline runs at least one block ahead of the hardware pipeline. The stages of the pipeline may each include a hardware pipeline component that performs one or more operations on a current block at the stage. At least one stage of the pipeline may also include a software pipe…
Who is the assignee on this patent?
Apple Inc
What technology area does this patent fall under?
Primary CPC classification H04N19/436. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Dec 15 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).