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US-2024414942-A1 · Dec 12, 2024 · US
Semiconductor device and method for manufacturing semiconductor device
US9214565B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9214565-B2 |
| Application number | US-201414493383-A |
| Country | US |
| Kind code | B2 |
| Filing date | Sep 23, 2014 |
| Priority date | Nov 11, 2011 |
| Publication date | Dec 15, 2015 |
| Grant date | Dec 15, 2015 |
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- Title
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Abstract
Official abstract text for this publication.
Provided is a miniaturized transistor having high electrical characteristics. The transistor includes a source electrode layer in contact with one side surface of the oxide semiconductor layer in the channel-length direction and a drain electrode layer in contact with the other side surface thereof. The transistor further includes a gate electrode layer in a region overlapping with a channel formation region with a gate insulating layer provided therebetween and a conductive layer having a function as part of the gate electrode layer in a region overlapping with the source electrode layer or the drain electrode layer with the gate insulating layer provided therebetween and in contact with a side surface of the gate electrode layer. With such a structure, an Lov region is formed with a scaled-down channel length maintained.
First claim
Opening claim text (preview).
What is claimed is: 1. A semiconductor device comprising: a source electrode layer and a drain electrode layer; an oxide semiconductor layer comprising a first impurity region, a second impurity region, and a channel formation region sandwiched between the first impurity region and the second impurity region, wherein a side surface of the first impurity region is in contact with and under the source electrode layer in a channel-length direction and a side surface of the second i…
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Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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Frequently asked questions
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- What does patent US9214565B2 cover?
- Provided is a miniaturized transistor having high electrical characteristics. The transistor includes a source electrode layer in contact with one side surface of the oxide semiconductor layer in the channel-length direction and a drain electrode layer in contact with the other side surface thereof. The transistor further includes a gate electrode layer in a region overlapping with a channel fo…
- Who is the assignee on this patent?
- Semiconductor Energy Lab
- What technology area does this patent fall under?
- Primary CPC classification H10D30/6755. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Dec 15 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).