Gallium nitride transistor with a hybrid aluminum oxide layer as a gate dielectric

Patent metadata

Field	Value
Publication number	US-9214539-B2
Application number	US-201314016328-A
Country	US
Kind code	B2
Filing date	Sep 3, 2013
Priority date	Sep 3, 2013
Publication date	Dec 15, 2015
Grant date	Dec 15, 2015

Abstract

Some embodiments of the present disclosure relates to a hybrid gate dielectric layer that has good interface and bulk dielectric properties. Surface traps can degrade device performance and cause large threshold voltage shifts in III-N HEMTs. This disclosure uses a hybrid ALD (atomic layer deposited)-oxide layer which is a combination of H2O-based and O3/O2-based oxide layers that provide both good interface and good bulk dielectric properties to the III-N device. The H2O-based oxide layer provides good interface with the III-N surface, whereas the O3/O2-based oxide layer provides good bulk properties.

First claim

What is claimed is:

1. A III-N (tri nitride) semiconductor device, comprising:
a buffer layer disposed above a substrate;
a crystalline or poly crystalline III-N layer disposed above the buffer layer;
a source region located at a first location in or on the crystalline or poly crystalline III-N layer;
a drain region located at a second location in or on the crystalline or poly crystalline III-N layer, wherein the second location is laterally disposed and separated from the…

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chiu Han-Chin
• Wong King-Yuen
• Tsai Cheng-Yuan
• Tsai Chia-Shiung
• Chen Xiaomeng

Classifications

• H10D64/691

  Electricity · mapped topic

• H10D64/516

  Electricity · mapped topic

• H10D64/685

  Electricity · mapped topic

• H10D62/8503

  Electricity · mapped topic

• H10D62/40

  Electricity · mapped topic