Semiconductor device
US-12057459-B2 · Aug 6, 2024 · US
Array substrate and display device
US9214482B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9214482-B2 |
| Application number | US-201314089841-A |
| Country | US |
| Kind code | B2 |
| Filing date | Nov 26, 2013 |
| Priority date | Nov 26, 2012 |
| Publication date | Dec 15, 2015 |
| Grant date | Dec 15, 2015 |
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Abstract
Official abstract text for this publication.
An array substrate and a display device includes: a base substrate; a TFT, a gate line, a data line and a pixel electrode formed on the base substrate, the TFT includes: a bottom gate, a first gate insulating layer, an active layer, a second gate insulating layer, a top gate, a gate isolation layer and a source electrode and a drain electrode sequentially formed on the base substrate; wherein, the source electrode and the drain electrode are in contact with the active layer through a first via hole and a second via hole passing through the gate isolation layer and the second insulating layer, respectively; the pixel electrode is in contact with the drain electrode.
First claim
Opening claim text (preview).
The invention claimed is: 1. An array substrate, comprising: a base substrate; and a TFT, a gate line, a data line and a pixel electrode formed on the base substrate, wherein the TFT includes: a bottom gate, a first gate insulating layer, an active layer, a second gate insulating layer, a top gate, a gate isolation layer and a source electrode and a drain electrode sequentially formed on the base substrate; wherein, the source electrode and the drain electrode are in contact…
Assignees
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Classifications
Electricity · mapped topic
Physics · mapped topic
- H10D30/6734Primary
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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Frequently asked questions
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- What does patent US9214482B2 cover?
- An array substrate and a display device includes: a base substrate; a TFT, a gate line, a data line and a pixel electrode formed on the base substrate, the TFT includes: a bottom gate, a first gate insulating layer, an active layer, a second gate insulating layer, a top gate, a gate isolation layer and a source electrode and a drain electrode sequentially formed on the base substrate; wherein, …
- Who is the assignee on this patent?
- Boe Technology Group Co Ltd
- What technology area does this patent fall under?
- Primary CPC classification H10D30/6734. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Dec 15 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).