Eutectic solder structure for chip

Patent metadata

Field	Value
Publication number	US-9214443-B2
Application number	US-201414272468-A
Country	US
Kind code	B2
Filing date	May 7, 2014
Priority date	Oct 17, 2013
Publication date	Dec 15, 2015
Grant date	Dec 15, 2015

Abstract

The present invention provides a eutectic solder structure for a chip including a substrate and a solder structure on the substrate. The solder structure includes an alternate lamination of a plurality of first metal layers and a plurality of second metal layers, wherein each second metal layer has a continuous region and a plurality of openings and the melting point of the plurality of second metal layers is higher than that of the plurality of first metal layers. The eutectic solder structure for a chip also includes a chip on the solder structure, wherein the chip is bonded to the substrate by a eutectic reaction of the solder structure.

First claim

What is claimed is:

1. A eutectic solder structure for a chip, comprising:
a substrate;
a solder structure on the substrate, wherein the solder structure includes an alternate lamination of a plurality of first metal layers and a plurality of second metal layers, wherein each second metal layer has a continuous region and a plurality of openings, and the melting point of the plurality of second metal layers is higher than that of the plurality of first metal layers, and wherein the orthographic projections of the openings of different second metal layers on the substrate are misaligned with each other; and
a chip on the solder structure, wherein the chip is bonded to the substrate by an eutectic reaction of the solder structure.

2. The eutectic solder structure for a chip as claimed in claim 1 , wherein a total basal area of the plurality of openings of each second metal layer is greater than a half of an area of the continuous region of each second metal layer.

3. The eutectic solder structure for a chip as claimed in claim 2 , wherein a total basal area of the plurality of openings of each second metal layer is less than nine-tenths ofthe area of the continuous region of each second metal layer.

4. The eutectic solder structure for a chip as claimed in claim 1 , wherein the shape of the plurality of openings of the plurality of second metal layers is circle, and a horizontal offset distance between the plurality of openings of adjacent second metal layers is less than or equal to the diameter of the largest opening of the plurality of openings of the plurality of the second metal layers.

5. The eutectic solder structure for a chip as claimed in claim 1 , wherein the shape of the plurality of openings of the plurality of second metal layers is rectangle, and a horizontal offset distance between the plurality of openings of adjacent second metal layers is less than or equal to the side lengths of the largest opening of the plurality of openings of the plurality of the second metal layers.

6. The eutectic solder structure for a chip as claimed in claim 1 , wherein the solder structure includes three first metal layers and two second metal layers, and one of the first metal layers is in direct contact with the substrate.

7. The eutectic solder structure for a chip as claimed in claim 1 , wherein the plurality of first metal layers and the plurality of second metal layers are selected from tin, copper, bismuth, gold, silver, nickel, or an alloy thereof.

8. The eutectic solder structure for a chip as claimed in claim 1 , further comprising an adhesion layer disposed between the solder structure and the chip.

Assignees

• Lextar Electronics Corp

Inventors

• Chen Yi-Jyun

Classifications

• H10W90/736

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W72/07355

  changes in materials · CPC title

• H10W72/07354

  changes in dispositions · CPC title

• H10W72/07353

  changes in shapes · CPC title