Semiconductor DRAM with non-linear word line discharge

Patent metadata

Field	Value
Publication number	US-9214218-B2
Application number	US-201213420345-A
Country	US
Kind code	B2
Filing date	Mar 14, 2012
Priority date	Mar 14, 2011
Publication date	Dec 15, 2015
Grant date	Dec 15, 2015

Abstract

Disclosed herein a device that includes a memory cell array including plurality of word lines, a plurality of bit lines each intersecting the word lines and a plurality of memory cells each disposed at an associated one of intersections of the word and bit lines, and the device further includes a driver configured to drive a selected one of the word lines from an inactive level to an active and to drive the selected one of the word lines from the active level to an intermediate level at a first rate and from the intermediated level to the inactive level at a second rate. The intermediate level is between the active and inactive levels, and the first rate is greater than the second rate.

First claim

What is claimed is:

1. A semiconductor device comprising:
first and second memory cell arrays arranged side by side in a first direction, each of said first and said second memory cell arrays comprising a memory cell mat that includes a word line and a bit line, a sub-word driver circuit that drives said word line, and a first control unit that controls said sub-word driver circuit; and
a first region that is disposed between said first memory cell array and said second memory c…

Assignees

• Kajigaya Kazuhiko
• Ps4 Luxco Sarl

Inventors

• Kajigaya Kazuhiko

Classifications

• G11C11/4085 Primary

  Physics · mapped topic

• G11C11/4094

  Physics · mapped topic

• G11C8/08

  Physics · mapped topic

• G11C11/4097

  Physics · mapped topic