Flexible arbitration scheme for multi endpoint atomic accesses in multicore systems

Patent metadata

Field	Value
Publication number	US-9213656-B2
Application number	US-201314061470-A
Country	US
Kind code	B2
Filing date	Oct 23, 2013
Priority date	Oct 24, 2012
Publication date	Dec 15, 2015
Grant date	Dec 15, 2015

Abstract

The MSMC (Multicore Shared Memory Controller) described is a module designed to manage traffic between multiple processor cores, other mastering peripherals or DMA, and the EMIF (External Memory InterFace) in a multicore SoC. The invention unifies all transaction sizes belonging to a slave previous to arbitrating the transactions in order to reduce the complexity of the arbitration process and to provide optimum bandwidth management among all masters. Two consecutive slots are assigned per cache line access to automatically guarantee the atomicity of all transactions within a single cache line. The need for synchronization among all the banks of a particular SRAM is eliminated, as synchronization is accomplished by assigning back to back slots.

First claim

What is claimed is:

1. A Multicore Shared Memory Controller (MSMC) comprising:
a plurality of CPU interfaces for connection to respective central processing units for receiving CPU transaction requests;
at least one slave interface for connection to a corresponding slave device serving as a shared resource;
a multicore shared memory controller datapath connected to said plurality of CPU interfaces and said at least one slave interface, said multicore shared memory controller d…

Assignees

• Texas Instruments Inc

Inventors

• Chirca Kai
• Pierson Matthew D

Classifications

• G06F12/084 Primary

  Physics · mapped topic

• G06F3/061

  Physics · mapped topic

• G06F13/1668 Primary

  Physics · mapped topic

• G06F13/1652

  Physics · mapped topic

• G06F3/064

  Physics · mapped topic