Cache management using shared cache line storage
US-2024241830-A1 · Jul 18, 2024 · US
Broadcast messaging and acknowledgment messaging for power management in a multiprocessor system
US9213643B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9213643-B2 |
| Application number | US-201313799268-A |
| Country | US |
| Kind code | B2 |
| Filing date | Mar 13, 2013 |
| Priority date | Mar 13, 2013 |
| Publication date | Dec 15, 2015 |
| Grant date | Dec 15, 2015 |
How to read this patent
A practical reading order for non-experts. Skip the full description unless you need deep technical detail.
- Title
What the patent document calls the invention.
- Abstract
A short plain-language summary of the technical disclosure.
- Assignees and inventors
Who owns or filed the patent and who is credited as inventor.
- Key dates
Filing, priority, publication, and grant dates set the timeline.
- First independent claim
The legal scope of protection — read this for what is actually claimed.
- CPC / IPC classifications
Technology tags used to group this patent with similar filings.
- Citations and related patents
Prior art links and similar publications in this corpus.
Abstract
Official abstract text for this publication.
Various aspects provide for implementing a cache coherence protocol. A system comprises at least one processing component and a centralized controller. The at least one processing component comprises a cache controller. The cache controller is configured to manage a cache memory associated with a processor. The centralized controller is configured to communicate with the cache controller based on a power state of the processor.
First claim
Opening claim text (preview).
What is claimed is: 1. A system, comprising: at least one processing component that comprises a cache controller, the cache controller being configured for managing a cache memory associated with a processor; and a centralized controller configured for storing a power state of the processor, storing one or more other power states associated with one or more other processors, and communicating with the cache controller based on the power state of the processor.…
Assignees
Inventors
Classifications
- G06F12/0833Primary
Physics · mapped topic
Physics · mapped topic
Physics · mapped topic
Cross-Sectional Technologies · mapped topic
Patent family
Related publications grouped by family.
External sources
Next steps
Free tools are coming soon. Tell us what you want to track and we'll notify you.
Frequently asked questions
Answers are generated from the same data shown on this page.
- What does patent US9213643B2 cover?
- Various aspects provide for implementing a cache coherence protocol. A system comprises at least one processing component and a centralized controller. The at least one processing component comprises a cache controller. The cache controller is configured to manage a cache memory associated with a processor. The centralized controller is configured to communicate with the cache controller based …
- Who is the assignee on this patent?
- Kruckemyer David Alan, Favor John Gregory, Applied Micro Circuits Corp
- What technology area does this patent fall under?
- Primary CPC classification G06F12/0833. Mapped technology areas include Physics.
- When was this patent published?
- Publication date Tue Dec 15 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).