Flash translation layer with lower write amplification

Patent metadata

Field	Value
Publication number	US-9213633-B2
Application number	US-201313889521-A
Country	US
Kind code	B2
Filing date	May 8, 2013
Priority date	Apr 30, 2013
Publication date	Dec 15, 2015
Grant date	Dec 15, 2015

Abstract

A method of associating a logical block address with a physical location in a non-volatile memory includes (A) in response to a write request comprising a respective logical block address in a logical block address space and respective data to be written to the non-volatile memory, determining a physical location in the non-volatile memory to store the respective data of the write request, (B) adding an entry to a journal, such that the added entry trails any entries already in the journal and the added entry has a respective logical block address field set to the respective logical block address of the write request and a respective physical location field set to the determined physical location, and (C) updating one of a plurality of second-level map pages in a two-level map according to the respective logical block address of the write request with the determined physical location.

First claim

The invention claimed is:

1. A method of associating a logical block address space with a physical address space of a non-volatile memory comprising:
in response to a write request comprising a respective logical block address in the logical block address space and respective data to be written to the non-volatile memory, determining a physical location in the non-volatile memory to store the respective data of the write request;
adding an entry to a journal, the added entry tra…

Assignees

• Seagate Technology Llc

Inventors

• Canepa Timothy L
• Cohen Earl T
• Tang Alex G

Classifications

• G06F2212/7201

  Physics · mapped topic

• G06F12/0246 Primary

  Physics · mapped topic