Block management method, memory controller and memory stoarge apparatus

US9213629B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9213629-B2
Application numberUS-201113233034-A
CountryUS
Kind codeB2
Filing dateSep 15, 2011
Priority dateJul 13, 2011
Publication dateDec 15, 2015
Grant dateDec 15, 2015

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  2. Abstract

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  5. First independent claim

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Abstract

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A block management method for a rewritable non-volatile memory module having a plurality of physical blocks, and a memory controller and memory storage apparatus using the same are provided. The method includes logically grouping the physical blocks at least into a data area, a free area and a replacement area and configuring a plurality of logical blocks for mapping to the physical blocks of the data area. The method also includes assigning bad physical blocks into the data area and marking the logical blocks mapping to the bad physical blocks as bad logical addresses, thereby forbidding the access of the logical blocks mapping to the bad physical blocks. According, the method can effectively use the rewritable non-volatile memory module having too many bad physical blocks to store data.

First claim

Opening claim text (preview).

What is claimed is: 1. A block management method for a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module has a plurality of physical blocks, the block management method comprising: logically grouping the physical blocks into at least a data area, a spare area and a replacement area, wherein the physical blocks of the data area includes at least one bad physical block; configuring a plurality of logical blocks for mapping to the physical blo…

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What does patent US9213629B2 cover?
A block management method for a rewritable non-volatile memory module having a plurality of physical blocks, and a memory controller and memory storage apparatus using the same are provided. The method includes logically grouping the physical blocks at least into a data area, a free area and a replacement area and configuring a plurality of logical blocks for mapping to the physical blocks of t…
Who is the assignee on this patent?
Yeh Chih-Kang, Phison Electronics Corp
What technology area does this patent fall under?
Primary CPC classification G06F12/0246. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Dec 15 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).