Memory performance evaluation using address mapping information
US-2024394164-A1 · Nov 28, 2024 · US
Non-volatile memory with block erasable locations
US9213627B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9213627-B2 |
| Application number | US-15897806-A |
| Country | US |
| Kind code | B2 |
| Filing date | Dec 13, 2006 |
| Priority date | Dec 21, 2005 |
| Publication date | Dec 15, 2015 |
| Grant date | Dec 15, 2015 |
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Abstract
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A main memory ( 10 ) comprises a plurality of physical blocks of memory locations. The main memory ( 10 ) supports erasing of at least a physical block at a time. Pointer information is stored in a subset ( 40, 42 ) of the blocks for use to identify respective ones of the physical blocks that are assigned to respective functions. Successive versions of the pointing information are stored at mutually different memory locations initially in a first block ( 40 ) in the subset ( 40, 42 ). A subsequent version of the pointing information that is more recent than the successive versions is stored in a second block ( 42 ) of the subset ( 40, 42 ) at least after the first block ( 40 ) has been filled. The first block ( 40 ) is erased after storing the subsequent version. On start up of the main memory the pointing information is recovered by testing which of the blocks of the subset ( 40, 42 ) contains a most recent version of the pointing information.
First claim
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The invention claimed is: 1. A memory apparatus, the apparatus comprising: a non-volatile main memory circuit that comprises a plurality of physical blocks of memory locations, the main memory supporting erasing of at least a physical block at a time; and a mapping control circuit configured and arranged to maintain pointing information for use to identify respective ones of the physical blocks that are assigned to respective functions, to define a subset of the physical blocks…
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- G06F12/0246Primary
Physics · mapped topic
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Frequently asked questions
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- What does patent US9213627B2 cover?
- A main memory ( 10 ) comprises a plurality of physical blocks of memory locations. The main memory ( 10 ) supports erasing of at least a physical block at a time. Pointer information is stored in a subset ( 40, 42 ) of the blocks for use to identify respective ones of the physical blocks that are assigned to respective functions. Successive versions of the pointing information are stored at mut…
- Who is the assignee on this patent?
- Van Acht Victor M G, Lambert Nicolaas, Nxp Bv
- What technology area does this patent fall under?
- Primary CPC classification G06F12/0246. Mapped technology areas include Physics.
- When was this patent published?
- Publication date Tue Dec 15 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).