Architecture for managing asynchronous resets in a system-on-a-chip
US-2024192745-A1 · Jun 13, 2024 · US
US9209796B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9209796-B2 |
| Application number | US-201414181013-A |
| Country | US |
| Kind code | B2 |
| Filing date | Feb 14, 2014 |
| Priority date | Sep 29, 2009 |
| Publication date | Dec 8, 2015 |
| Grant date | Dec 8, 2015 |
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In some embodiments, a reset circuit for an electronic circuit equipped with a backup power capacitor includes a first detector arranged to detect a predetermined first voltage of the backup capacitor, a second detector arranged to detect a predetermined second voltage of the backup capacitor, the second voltage being lower than the first voltage, and a controller arranged to control an output of a reset request signal based on detection results of the first detector and the second detector. The controller is configured to output the reset request signal when the first detector detects the first voltage after the second detector detected the second detector.
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What is claimed is: 1. A method for operating a circuit, comprising: providing a first voltage on a power supply line from a backup energy storage element in response to a main power supply becoming inactive, the first voltage at a first voltage level; generating a first detection signal in response to the first voltage from the backup energy storage element reaching a second voltage level; generating a second detection signal in response to the first voltage from the backup…
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