Pass-through 3D interconnect for microelectronic dies and associated systems and methods

US9209158B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9209158-B2
Application numberUS-201113335619-A
CountryUS
Kind codeB2
Filing dateDec 22, 2011
Priority dateDec 28, 2007
Publication dateDec 8, 2015
Grant dateDec 8, 2015

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  1. Title

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  2. Abstract

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  4. Key dates

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  5. First independent claim

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Abstract

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Pass-through 3D interconnects and microelectronic dies and systems of stacked dies that include such interconnects are disclosed herein. In one embodiment, a system of stacked dies includes a first microelectronic die having a substrate, a metal substrate pad, and a first integrated circuit electrically coupled to the substrate pad. A pass-through 3D interconnect extends between front and back sides of the substrate, including through the substrate pad. The pass-through interconnect is electrically isolated from the substrate pad and electrically coupled to a second integrated circuit of a second microelectronic die attached to the back side of the substrate. In another embodiment, the first integrated circuit is a first memory device and the second integrated circuit is a second memory device, and the system uses the pass-through interconnect as part of an independent communication path to the second memory device.

First claim

Opening claim text (preview).

We claim: 1. A method of manufacturing a stacked system of microelectronic dies, the method comprising: forming a substrate pad at a front side of a first microelectronic die; forming first and second metal traces at the front side, wherein the first trace is connected to the substrate pad; forming a hole having a sidewall that extends through the substrate pad and the first microelectronic die to a second side of the first microelectronic die opposite the first side; lining…

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What does patent US9209158B2 cover?
Pass-through 3D interconnects and microelectronic dies and systems of stacked dies that include such interconnects are disclosed herein. In one embodiment, a system of stacked dies includes a first microelectronic die having a substrate, a metal substrate pad, and a first integrated circuit electrically coupled to the substrate pad. A pass-through 3D interconnect extends between front and back …
Who is the assignee on this patent?
Pratt David S, Kirby Kyle K, Ray Dewali, and 1 more
What technology area does this patent fall under?
Primary CPC classification H10W90/00. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Dec 08 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).