Package substrate and semiconductor package including the same
US-2024429153-A1 · Dec 26, 2024 · US
US9209158B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9209158-B2 |
| Application number | US-201113335619-A |
| Country | US |
| Kind code | B2 |
| Filing date | Dec 22, 2011 |
| Priority date | Dec 28, 2007 |
| Publication date | Dec 8, 2015 |
| Grant date | Dec 8, 2015 |
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Pass-through 3D interconnects and microelectronic dies and systems of stacked dies that include such interconnects are disclosed herein. In one embodiment, a system of stacked dies includes a first microelectronic die having a substrate, a metal substrate pad, and a first integrated circuit electrically coupled to the substrate pad. A pass-through 3D interconnect extends between front and back sides of the substrate, including through the substrate pad. The pass-through interconnect is electrically isolated from the substrate pad and electrically coupled to a second integrated circuit of a second microelectronic die attached to the back side of the substrate. In another embodiment, the first integrated circuit is a first memory device and the second integrated circuit is a second memory device, and the system uses the pass-through interconnect as part of an independent communication path to the second memory device.
Opening claim text (preview).
We claim: 1. A method of manufacturing a stacked system of microelectronic dies, the method comprising: forming a substrate pad at a front side of a first microelectronic die; forming first and second metal traces at the front side, wherein the first trace is connected to the substrate pad; forming a hole having a sidewall that extends through the substrate pad and the first microelectronic die to a second side of the first microelectronic die opposite the first side; lining…
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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