Method for forming a fine pattern using isotropic etching

Patent metadata

Field	Value
Publication number	US-9209108-B2
Application number	US-201313917207-A
Country	US
Kind code	B2
Filing date	Jun 13, 2013
Priority date	Sep 30, 2006
Publication date	Dec 8, 2015
Grant date	Dec 8, 2015

Abstract

A method for forming a fine pattern using isotropic etching, includes the steps of forming an etching layer on a semiconductor substrate, and coating a photoresist layer on the etching layer, performing a lithography process with respect to the etching layer coated with the photoresist layer, and performing a first isotropic etching process with respect to the etching layer including a photoresist pattern formed through the lithography process, depositing a passivation layer on the etching layer including the photoresist pattern, and performing a second isotropic etching process with respect to the passivation layer. The second isotropic etching process is directly performed without removing the predetermined portion of the passivation layer.

First claim

The invention claimed is:

1. A semiconductor device, comprising:
a substrate; and
an internal lead formed on the substrate and having a fine pattern, wherein the internal lead includes an upper surface, a lower surface and a side surface connecting the upper surface to the lower surface, the side surface extending substantially continuously without a step from the upper surface to the lower surface,
wherein a width of the internal lead gradually narrows from a lower width to an upper width such that the upper width is less than the lower width of the internal lead, and a ratio of the upper width/lower width is over 40%, and
wherein the side surface of the internal lead has an upper portion and a lower portion, and the semiconductor device further comprises:
a passivation layer formed directly on upper portion of the side surface of the internal lead and not directly on the lower portion of the side surface of the internal lead such that the passivation layer leaves the lower portion of the side surface of the internal lead exposed.

2. The semiconductor device according to claim 1 ,
wherein the internal lead has a ratio of the upper width/lower width not less than 40% and not more than 90%.

3. The semiconductor device according to claim 1 , wherein the side surface has a curved shape.

4. The semiconductor device according to claim 1 , wherein the passivation layer is an organic layer.

5. The semiconductor device according to claim 1 , wherein the fine pattern has a ratio of the upper width/lower width not less than 80%.

6. A semiconductor device, comprising:
a substrate; and
an internal lead having a fine pattern, the internal lead comprising an upper portion to which a first isotropic etching process has been applied and a lower portion to which a second isotropic etching process has been applied; and
a passivation layer formed directly on the upper portion of the internal lead and not directly on the lower portion of the internal lead such that the passivation layer leaves the lower portion of the internal lead exposed,
wherein a width of the internal lead gradually narrows from a lower width to an upper width such that the upper width is less than the lower width of the internal lead, and a ratio of the upper width to the lower width is over 40%.

7. The semiconductor device according to claim 6 , wherein the passivation layer is an organic layer.

8. The semiconductor device according to claim 6 , wherein the fine pattern has a ratio of the upper width/lower width not less than 80%.

9. The semiconductor device according to claim 6 , wherein the internal lead includes an upper surface, a lower surface and a side surface connecting the upper surface to the lower surface, and the side surface extends substantially continuously without a step from the upper surface to the lower surface.

10. The semiconductor device according to claim 9 , wherein the side surface has a curved shape.

Assignees

• Lg Innotek Co Ltd

Inventors

• Lee Sang-Yu
• Paik Jee-Heum
• Kim Soo-Hong
• Yoo Chang-Woo
• Yoon Sung-Woon

Classifications

• H10P50/667

  by liquid etching only · CPC title

• H10P50/283 Primary

  by chemical means · CPC title

• H10P50/73

  using masks for insulating materials · CPC title

• H10W72/00 Primary

  Interconnections or connectors in packages · CPC title

• H05K3/06

  the conductive material being removed chemically or electrolytically, e.g. by photo-etch process {(semi-additive methods H05K3/108)} · CPC title