Semiconductor devices having a seal ring
US-2024413245-A1 · Dec 12, 2024 · US
Conductor layout technique to reduce stress-induced void formations
US9209079B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9209079-B2 |
| Application number | US-201414486012-A |
| Country | US |
| Kind code | B2 |
| Filing date | Sep 15, 2014 |
| Priority date | May 22, 2006 |
| Publication date | Dec 8, 2015 |
| Grant date | Dec 8, 2015 |
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- Title
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Abstract
Official abstract text for this publication.
A semiconductor device is prepared by an annealing process to interconnect at least two components of the device by a conductor line surrounded by an insulator material. The annealing process results in formation of residual stresses within the conductor line and the insulator material. One or multiple notches are designed in the layout on a selective portion of the mask for patterning conductor line. The existence of the notch or notches on the selective portion generates extra stress components within the conductor line than would exist without the existence of the notch. The position of the notch is selected so that the extra stress components substantially counteract the residual stresses, thereby causing a net reduction in the residual stresses. The reduction in the residual stresses results in a corresponding mechanical stress migration and therefore improvement in the reliability of the device.
First claim
Opening claim text (preview).
What is claimed is: 1. A method comprising: providing a mask including a plurality of mask lines including at least a first mask line including at least one notch shape; fabricating a portion of a semiconductor circuit using the mask to form a plurality of conductive lines corresponding to the plurality of mask lines and including a first conductive line corresponding to the first mask line, the first conductive line including parallel edges extending in a lengthwise direction and…
Assignees
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Classifications
Electricity · mapped topic
- H10W20/43Primary
Electricity · mapped topic
Electricity · mapped topic
- H10W20/023Primary
Electricity · mapped topic
Electricity · mapped topic
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Frequently asked questions
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- What does patent US9209079B2 cover?
- A semiconductor device is prepared by an annealing process to interconnect at least two components of the device by a conductor line surrounded by an insulator material. The annealing process results in formation of residual stresses within the conductor line and the insulator material. One or multiple notches are designed in the layout on a selective portion of the mask for patterning conducto…
- Who is the assignee on this patent?
- Taiwan Semiconductor Mfg Co Ltd
- What technology area does this patent fall under?
- Primary CPC classification H10W20/43. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Dec 08 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).