Semiconductor device

US9207751B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9207751-B2
Application numberUS-201313778218-A
CountryUS
Kind codeB2
Filing dateFeb 27, 2013
Priority dateMar 1, 2012
Publication dateDec 8, 2015
Grant dateDec 8, 2015

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

The semiconductor device includes a CPU core having functions of a control unit, an arithmetic unit, and a register; a first memory device including a plurality of blocks each including one or a plurality of rows of memory cells; a second memory device copying data that is to be treated in the CPU core from a first block selected by the CPU core from the plurality of blocks included in the first memory device, and storing the data; a plurality of switches controlling supply of power supply voltage to the respective blocks; a memory management unit recognizing an address of the first block; and a power controller turning off one of the plurality of switches using the address to stop supply of the power supply voltage to a second block of the plurality of blocks which is different from the first block.

First claim

Opening claim text (preview).

What is claimed is: 1. A semiconductor device comprising: a memory device comprising a first block, a second block, a first decoder being electrically connected to the first block, and a second decoder being electrically connected to the second block, the first block and the second block each including at least one row of memory cells; a cache configured to temporarily store data from the first block; a first switch between the first block and a first power supply line, and co…

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Frequently asked questions

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What does patent US9207751B2 cover?
The semiconductor device includes a CPU core having functions of a control unit, an arithmetic unit, and a register; a first memory device including a plurality of blocks each including one or a plurality of rows of memory cells; a second memory device copying data that is to be treated in the CPU core from a first block selected by the CPU core from the plurality of blocks included in the firs…
Who is the assignee on this patent?
Semiconductor Energy Lab
What technology area does this patent fall under?
Primary CPC classification G06F1/3275. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Dec 08 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).