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US-2024414942-A1 · Dec 12, 2024 · US
US9202924B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9202924-B2 |
| Application number | US-201414147594-A |
| Country | US |
| Kind code | B2 |
| Filing date | Jan 6, 2014 |
| Priority date | Jan 11, 2013 |
| Publication date | Dec 1, 2015 |
| Grant date | Dec 1, 2015 |
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A semiconductor device comprising a gate electrode; an insulating layer in electrical connection with the gate electrode; a source electrode and a drain electrode; and a semiconducting channel layer configured to selectively allow electrically connection between the source electrode and the drain electrode based on the voltage on the gate electrode; wherein the semiconducting channel layer comprises metal nanoparticles; and the semiconducting channel layer is in contact with the source electrode, the drain electrode and the insulating layer. A method of manufacturing the semiconductor device of the present invention is also disclosed.
Opening claim text (preview).
What is claimed is: 1. A semiconductor device comprising a) a gate electrode; b) an insulating layer in electrical connection with said gate electrode; c) a source electrode and a drain electrode; and d) a semiconducting channel layer configured to selectively allow electrically connection between said source electrode and said drain electrode based on the voltage on said gate electrode; wherein said semiconducting channel layer comprises metal nanoparticles and metal oxide nanoparticles; wherein said semiconducting channel layer is in contact with said source electrode, said drain electrode and said insulating layer; and wherein said metal nanoparticles are selected from a group consisting of Au, Ag, Pd, Pt and any combinations thereof and said metal oxide nanoparticles are selected from a group of ZnO and CuO; wherein said metal nanoparticles and said metal oxide nanoparticles form an array of self-assembly nanostructure; wherein said array of self-assembly nanostructure forms a monolayer. 2. The semiconductor device according to claim 1 , wherein said semiconductor device is a thin film transistor of an inverter used in a ring oscillator of an RFID tag. 3. A method of manufacturing a semiconductor device comprising the steps of: a) providing a nanoparticle solution comprising metal nanoparticles and metal oxide nanoparticles; b) allowing said nanoparticles to undergo self-assembly to form a 2D self-assembled nanoparticles monolayer on said nanoparticle solution; c) forming said array of nanoparticles onto a substrate to form a semiconducting channel layer; and d) forming source and drain electrodes in contact with said semiconducting channel layer; wherein said metal nanoparticles are selected from the group consisting of Au, Ag, Pd, Pt and any combinations thereof; and wherein said metal oxide nanoparticles are selected from a group consisting of ZnO and CuO. 4. The semiconductor device of claim 1 , wherein said metal oxide nanoparticles are CuO. 5. The method of manufacturing a semiconductor device of claim 3 , wherein said metal oxide nanoparticles are CuO. 6. The method of manufacturing a semiconductor device of claim 3 further comprises the step of preparing a nanoparticle solution comprising H 2 PdCl 4 , L-ascorbic acid and PVP.
Subject matter not provided for in other groups of this subclass · CPC title
of IGFETs (IGFETs having buried channels H10D30/637) · CPC title
Nanostructure semiconductor bodies · CPC title
characterised by the materials · CPC title
characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715) · CPC title
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