RFID tags based on self-assembly nanoparticles

US9202924B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9202924-B2
Application numberUS-201414147594-A
CountryUS
Kind codeB2
Filing dateJan 6, 2014
Priority dateJan 11, 2013
Publication dateDec 1, 2015
Grant dateDec 1, 2015

How to read this patent

A practical reading order for non-experts. Skip the full description unless you need deep technical detail.

  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

    Who owns or filed the patent and who is credited as inventor.

  4. Key dates

    Filing, priority, publication, and grant dates set the timeline.

  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

    Prior art links and similar publications in this corpus.

Abstract

Official abstract text for this publication.

A semiconductor device comprising a gate electrode; an insulating layer in electrical connection with the gate electrode; a source electrode and a drain electrode; and a semiconducting channel layer configured to selectively allow electrically connection between the source electrode and the drain electrode based on the voltage on the gate electrode; wherein the semiconducting channel layer comprises metal nanoparticles; and the semiconducting channel layer is in contact with the source electrode, the drain electrode and the insulating layer. A method of manufacturing the semiconductor device of the present invention is also disclosed.

First claim

Opening claim text (preview).

What is claimed is: 1. A semiconductor device comprising a) a gate electrode; b) an insulating layer in electrical connection with said gate electrode; c) a source electrode and a drain electrode; and d) a semiconducting channel layer configured to selectively allow electrically connection between said source electrode and said drain electrode based on the voltage on said gate electrode; wherein said semiconducting channel layer comprises metal nanoparticles and metal oxide nanoparticles; wherein said semiconducting channel layer is in contact with said source electrode, said drain electrode and said insulating layer; and wherein said metal nanoparticles are selected from a group consisting of Au, Ag, Pd, Pt and any combinations thereof and said metal oxide nanoparticles are selected from a group of ZnO and CuO; wherein said metal nanoparticles and said metal oxide nanoparticles form an array of self-assembly nanostructure; wherein said array of self-assembly nanostructure forms a monolayer. 2. The semiconductor device according to claim 1 , wherein said semiconductor device is a thin film transistor of an inverter used in a ring oscillator of an RFID tag. 3. A method of manufacturing a semiconductor device comprising the steps of: a) providing a nanoparticle solution comprising metal nanoparticles and metal oxide nanoparticles; b) allowing said nanoparticles to undergo self-assembly to form a 2D self-assembled nanoparticles monolayer on said nanoparticle solution; c) forming said array of nanoparticles onto a substrate to form a semiconducting channel layer; and d) forming source and drain electrodes in contact with said semiconducting channel layer; wherein said metal nanoparticles are selected from the group consisting of Au, Ag, Pd, Pt and any combinations thereof; and wherein said metal oxide nanoparticles are selected from a group consisting of ZnO and CuO. 4. The semiconductor device of claim 1 , wherein said metal oxide nanoparticles are CuO. 5. The method of manufacturing a semiconductor device of claim 3 , wherein said metal oxide nanoparticles are CuO. 6. The method of manufacturing a semiconductor device of claim 3 further comprises the step of preparing a nanoparticle solution comprising H 2 PdCl 4 , L-ascorbic acid and PVP.

Assignees

Inventors

Classifications

  • Subject matter not provided for in other groups of this subclass · CPC title

  • of IGFETs (IGFETs having buried channels H10D30/637) · CPC title

  • Nanostructure semiconductor bodies · CPC title

  • characterised by the materials · CPC title

  • characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715) · CPC title

Patent family

Related publications grouped by family.

External sources

Frequently asked questions

Answers are generated from the same data shown on this page.

What does patent US9202924B2 cover?
A semiconductor device comprising a gate electrode; an insulating layer in electrical connection with the gate electrode; a source electrode and a drain electrode; and a semiconducting channel layer configured to selectively allow electrically connection between the source electrode and the drain electrode based on the voltage on the gate electrode; wherein the semiconducting channel layer comp…
Who is the assignee on this patent?
Nano & Advanced Materials Inst Ltd
What technology area does this patent fall under?
Primary CPC classification H10D30/6755. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Dec 01 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).