Laminated ceramic electronic component and method of fabricating the same

Patent metadata

Field	Value
Publication number	US-9202625-B2
Application number	US-201213678364-A
Country	US
Kind code	B2
Filing date	Nov 15, 2012
Priority date	Jul 20, 2012
Publication date	Dec 1, 2015
Grant date	Dec 1, 2015

Abstract

There is provided a laminated ceramic electronic component, including a ceramic body including a dielectric layer; and first and second internal electrodes disposed to face each other, having the dielectric layer interposed therebetween within the ceramic body, wherein when a value of 1% is set to be D1, a value of 50% is set to be D50, and a value of 99% is set to be D99 in a cumulative distribution of dielectric grains by an average particle diameter thereof within the dielectric layer, 2≦D99/D50≦3 and 2≦D50/D1≦3 are satisfied. A high-capacity laminated ceramic electronic component may be implemented with improved adhesion between the dielectric layer and the internal electrode, and improved withstand voltage characteristics and excellent reliability may be implemented.

First claim

What is claimed is:

1. A laminated ceramic electronic component, comprising:
a ceramic body including a dielectric layer; and
first and second internal electrodes disposed to face each other, having the dielectric layer interposed therebetween within the ceramic body,
in a cumulative distribution of dielectric grains by an average particle diameter thereof within the dielectric layer, when a value of 1% is set to be D1, a value of 50% is set to be D50, and a value of 99% is set to be D99, 2≦D99/D50≦3 and 2≦D50/D1≦3 being satisfied.

2. The laminated ceramic electronic component of claim 1 , wherein an average thickness td of the dielectric layer satisfies 0.1 μm≦td≦0.5 μm.

3. The laminated ceramic electronic component of claim 1 , wherein the average thickness td of the dielectric layer and D50 in a value of 50% in the cumulative distribution of dielectric grains by an average particle diameter thereof satisfy the relationship of td/8≦D50≦td/3.

4. The laminated ceramic electronic component of claim 1 , wherein when an average roughness of the dielectric layer on a central line thereof is Ra, 5 nm≦Ra≦30 nm is satisfied.

5. The laminated ceramic electronic component of claim 1 , wherein a ceramic powder used for the dielectric layer includes a first ceramic powder and a second ceramic powder having an average particle diameter smaller than that of the first ceramic powder.

6. The laminated ceramic electronic component of claim 5 , wherein the average particle diameter of the first ceramic powder is 1.5 times to 4.5 times larger than that of the second ceramic powder.

7. The laminated ceramic electronic component of claim 5 , wherein the ceramic powder includes the first ceramic powder in an amount of 70 to 99 parts by weight and the second ceramic powder in an amount of 1 to 30 parts by weight.

8. A laminated ceramic electronic component, comprising:
a ceramic body including a dielectric layer; and
first and second internal electrodes disposed to face each other, having the dielectric layer interposed therebetween within the ceramic body,
in a cumulative distribution of dielectric grains by particle size within the dielectric layer, when an average thickness of the dielectric layer is td, 0.1 μm≦td≦0.5 μm, and when a value of 1% is set to be D1, a value of 50% is set to be D50, and a value of 99% is set to be D99, 2≦D99/D50≦3 and 2≦D50/D1≦3 being satisfied and td/8≦D50≦td/3 being satisfied.

9. The laminated ceramic electronic component of claim 8 , wherein when an average roughness of the dielectric layer on a central line thereof is Ra, 5 nm≦Ra≦30 nm is satisfied.

10. The laminated ceramic electronic component of claim 8 , wherein when an average thickness of the first and second internal electrodes is te, 0.1 μm≦te≦0.5 μm is satisfied.

11. The laminated ceramic electronic component of claim 8 , wherein the average thickness td of the dielectric layer is the average thickness of the dielectric layer in a cross-section taken in length and thickness directions of the ceramic body cut in a central portion in a width direction thereof.

12. The laminated ceramic electronic component of claim 8 , wherein a ceramic powder used for the dielectric layer includes a first ceramic powder and a second ceramic powder having an average particle diameter smaller than that of the first ceramic powder.

13. The laminated ceramic electronic component of claim 12 , wherein the average particle diameter of the first ceramic powder is 1.5 times to 4.5 times larger than that of the second ceramic powder.

14. The laminated ceramic electronic component of claim 12 , wherein the ceramic powder includes the first ceramic powder in an amount of 70 to 99 parts by weight and the second ceramic powder in an amount of 1 to 30 parts by weight.

15. A method of fabricating a laminated ceramic electronic component, comprising:
preparing a ceramic green sheet using slurry including a first ceramic powder and a second ceramic powder having an average particle diameter smaller than that of the first ceramic powder;
forming internal electrode patterns on the ceramic green sheet using a conductive metal paste; and
forming a ceramic body including a dielectric layer and first and second internal electrodes disposed to face each other, having the dielectric layer interposed therebetween, by laminating and sintering the ceramic green sheet,
in a cumulative distribution of dielectric grains by an average particle diameter thereof within the dielectric layer, when a value of 1% is set to be D1, a value of 50% is set to be D50, and a value of 99% is set to be D99, 2≦D99/D50≦3 and 2≦D50/D1≦3 being satisfied.

16. The method of claim 15 , wherein an average thickness td of the dielectric layer satisfies 0.1 μm≦td≦0.5 μm.

17. The method of claim 15 , wherein an average thickness td of the dielectric layer and D50 in a value of 50% in the cumulative distribution of the dielectric grains by an average particle diameter thereof satisfy the relationship of td/8≦D50≦td/3.

18. The method of claim 15 , wherein when an average roughness of the dielectric layer on a central line thereof is Ra, 5 nm≦Ra≦30 nm is satisfied.

19. The method of claim 15 , wherein the average particle diameter of the first ceramic powder is 1.5 times to 4.5 times larger than that of the second ceramic powder.

20. The method of claim 15 , wherein the first ceramic powder is contained in an amount of 70 to 99 parts by weight and the second ceramic powder is contained in an amount of 1 to 30 parts by weight, with respect to an overall amount of ceramic powder.

Assignees

• Samsung Electro Mech

Inventors

• Jeong Han Soung
• Kim Chang Hoon
• Kwon Sang Hoon
• Yoon Seok Hyun

Classifications

• C04B2235/785

  Submicron sized grains, i.e. from 0,1 to 1 micron · CPC title

• H01G4/30 Primary

  Stacked capacitors (H01G4/33 takes precedence) · CPC title

• C04B2235/5445

  submicron sized, i.e. from 0,1 to 1 micron · CPC title

• Y10T156/1092

  All laminae planar and face to face · CPC title

• C04B2235/5472

  Bimodal, multi-modal or multi-fraction · CPC title