Disaggregated server architecture for data centers

US9201837B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9201837-B2
Application numberUS-201313802046-A
CountryUS
Kind codeB2
Filing dateMar 13, 2013
Priority dateMar 13, 2013
Publication dateDec 1, 2015
Grant dateDec 1, 2015

How to read this patent

A practical reading order for non-experts. Skip the full description unless you need deep technical detail.

  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

    Who owns or filed the patent and who is credited as inventor.

  4. Key dates

    Filing, priority, publication, and grant dates set the timeline.

  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

    Prior art links and similar publications in this corpus.

Abstract

Official abstract text for this publication.

A system comprising a unified interconnect network, a plurality of process memory modules, and a plurality of processor modules configured to share access to the memory modules via the unified interconnect network. Data may be communicated between a plurality of processor modules and a plurality of shared resource pools via a unified interconnect network, wherein the communications comprise a protocol that is common to all resource pools, and wherein each resource pool comprises a plurality of resource modules each configured to perform a common function. Further, a network interface controller (NIC) module may be configured to receive data from a plurality of processor modules via a unified interconnect network, and provide core network connectivity to the processor modules.

First claim

Opening claim text (preview).

What is claimed is: 1. A system comprising: a unified interconnect network; a memory pool comprising a plurality of process memory modules configured to cache process data, wherein each process memory module in the memory pool is positioned in one of a plurality of memory blade servers; and a processor pool comprising a plurality of processor modules configured to share access to the process memory modules in the memory pool for caching the process data via the unified interco…

Assignees

Inventors

Classifications

Patent family

Related publications grouped by family.

External sources

Next steps

Free tools are coming soon. Tell us what you want to track and we'll notify you.

Frequently asked questions

Answers are generated from the same data shown on this page.

What does patent US9201837B2 cover?
A system comprising a unified interconnect network, a plurality of process memory modules, and a plurality of processor modules configured to share access to the memory modules via the unified interconnect network. Data may be communicated between a plurality of processor modules and a plurality of shared resource pools via a unified interconnect network, wherein the communications comprise a p…
Who is the assignee on this patent?
Futurewei Technologies Inc
What technology area does this patent fall under?
Primary CPC classification G06F15/17331. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Dec 01 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).