Memory interconnect network architecture for vector processor

Patent metadata

Field	Value
Publication number	US-9201828-B2
Application number	US-201213720624-A
Country	US
Kind code	B2
Filing date	Dec 19, 2012
Priority date	Oct 23, 2012
Publication date	Dec 1, 2015
Grant date	Dec 1, 2015

Abstract

The present disclosure provides a memory interconnection architecture for a processor, such as a vector processor, that performs parallel operations. An example processor may include a compute array that includes processing elements; a memory that includes memory banks; and a memory interconnect network architecture that interconnects the compute array to the memory. In an example, the memory interconnect network architecture includes a switch-based interconnect network and a non-switch based interconnect network. The processor is configured to synchronously load a first data operand to each of the processing elements via the switch-based interconnect network and a second data operand to each of the processing elements via the non-switch-based interconnect network.

First claim

What is claimed is:

1. A processor, comprising:
a compute array that includes processing elements;
a memory that includes memory banks; and
a memory interconnect network architecture that is to interconnect at least some of the processing elements to at least some of the memory banks, wherein the memory interconnect network architecture includes:
a switch-based interconnection network, and
a non-switch-based interconnection network,
wherein the processor is configured to…

Assignees

• Sanghai Kaushal
• Lerner Boris
• Perkins Michael G
• Redford John L
• Analog Devices Inc

Inventors

• Sanghai Kaushal
• Lerner Boris
• Perkins Michael G
• Redford John L

Classifications

• G06F9/3001 Primary

  Physics · mapped topic

• G06F9/3824

  Physics · mapped topic

• G06F9/30007

  Physics · mapped topic

• G06F13/4022

  Physics · mapped topic

• G06F13/40 Primary

  Physics · mapped topic