Mixed redundancy scheme for inter-die interconnects in a multichip package
US-2016363626-A1 · Dec 15, 2016 · US
US9201741B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9201741-B2 |
| Application number | US-201314063524-A |
| Country | US |
| Kind code | B2 |
| Filing date | Oct 25, 2013 |
| Priority date | Dec 13, 2012 |
| Publication date | Dec 1, 2015 |
| Grant date | Dec 1, 2015 |
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A storage device, includes: a plurality of controller modules; a bus disposed among the plurality of controller modules, the bus including a plurality of transmission paths; a detector configured to detect an error in data communication through the bus; and a connection controller configured to carry out partial fallback processing of the bus if the number of the errors has exceeded a given number.
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What is claimed is: 1. A storage device, comprising: a plurality of controller modules; a bus disposed among the plurality of controller modules, the bus including a plurality of transmission paths; a detector configured to detect one or more errors in data communication through the bus; and a connection controller configured to carry out partial fallback processing of the bus if when a number of the one or more errors has exceeded a given number, wherein the connection co…
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