Method for memory storage and access
US-2024126640-A1 · Apr 18, 2024 · US
US9201727B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9201727-B2 |
| Application number | US-201313741599-A |
| Country | US |
| Kind code | B2 |
| Filing date | Jan 15, 2013 |
| Priority date | Jan 15, 2013 |
| Publication date | Dec 1, 2015 |
| Grant date | Dec 1, 2015 |
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A system for providing error detection or correction on a data bus includes one or more caches coupled to a central processing unit and to a hub by one or more buses. The system also includes a plurality of arrays, each array disposed on one of the buses. Each of the arrays includes a plurality of storage cells disposed in an insensitive direction and an error control mechanism configured to detect an error in the plurality of storage cells.
Opening claim text (preview).
What is claimed is: 1. A system for providing error detection or correction on a data bus, the system comprising: one or more caches, wherein each cache is coupled to a central processing unit and to a hub by one or more data buses configured to transfer data between the one or more caches and the central processing unit; and a plurality of arrays, each array disposed on one of the one or more data buses, wherein each of the arrays comprises: a plurality of storage cells dispos…
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