Memory performance evaluation using address mapping information
US-2024394164-A1 · Nov 28, 2024 · US
Memory system
US9201717B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9201717-B2 |
| Application number | US-201414199808-A |
| Country | US |
| Kind code | B2 |
| Filing date | Mar 6, 2014 |
| Priority date | Mar 1, 2008 |
| Publication date | Dec 1, 2015 |
| Grant date | Dec 1, 2015 |
How to read this patent
A practical reading order for non-experts. Skip the full description unless you need deep technical detail.
- Title
What the patent document calls the invention.
- Abstract
A short plain-language summary of the technical disclosure.
- Assignees and inventors
Who owns or filed the patent and who is credited as inventor.
- Key dates
Filing, priority, publication, and grant dates set the timeline.
- First independent claim
The legal scope of protection — read this for what is actually claimed.
- CPC / IPC classifications
Technology tags used to group this patent with similar filings.
- Citations and related patents
Prior art links and similar publications in this corpus.
Abstract
Official abstract text for this publication.
A memory system includes a volatile first storing unit, a nonvolatile second storing unit in which data is managed in a predetermined unit, and a controller that writes data requested by a host apparatus in the second storing unit via the first storing unit and reads out data requested by the host apparatus from the second storing unit to the first storing unit and transfers the data to the host apparatus. The controller includes a management table for managing the number of failure areas in a predetermined unit that occur in the second storing unit and switches, according to the number of failure areas, an operation mode in writing data in the second storing unit from the host apparatus.
First claim
Opening claim text (preview).
What is claimed is: 1. A memory system comprising: a nonvolatile memory including a plurality of blocks; and a controller configured to count a number of bad blocks in the nonvolatile memory, wherein, in a case that the number of counted bad blocks in the nonvolatile memory has reached a first threshold, a warning indication is issued, in a case that the number of counted bad blocks in the nonvolatile memory has reached a second threshold, a data write operation to the nonvo…
Assignees
Inventors
Classifications
- G06F12/0246Primary
Physics · mapped topic
Physics · mapped topic
Physics · mapped topic
- G06F11/073Primary
Physics · mapped topic
Physics · mapped topic
Patent family
Related publications grouped by family.
External sources
Next steps
Free tools are coming soon. Tell us what you want to track and we'll notify you.
Frequently asked questions
Answers are generated from the same data shown on this page.
- What does patent US9201717B2 cover?
- A memory system includes a volatile first storing unit, a nonvolatile second storing unit in which data is managed in a predetermined unit, and a controller that writes data requested by a host apparatus in the second storing unit via the first storing unit and reads out data requested by the host apparatus from the second storing unit to the first storing unit and transfers the data to the hos…
- Who is the assignee on this patent?
- Toshiba Kk
- What technology area does this patent fall under?
- Primary CPC classification G06F12/0246. Mapped technology areas include Physics.
- When was this patent published?
- Publication date Tue Dec 01 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).