Patterning device defect detection systems and methods
US-2024210336-A1 · Jun 27, 2024 · US
Verification and modification method of rules of do-not-inspect regions, computer program, and apparatus for such verification and modification
US9201296B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9201296-B2 |
| Application number | US-92649610-A |
| Country | US |
| Kind code | B2 |
| Filing date | Nov 22, 2010 |
| Priority date | May 22, 2008 |
| Publication date | Dec 1, 2015 |
| Grant date | Dec 1, 2015 |
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Abstract
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A verification method and apparatus for do-not-inspect region rules include storing information specifying do-not-inspect regions, and storing a pixel unit size which defines a length of a single pixel unit. A minimum size verification process includes calculating sizes of do-not-inspect regions, and verifying whether a minimum size rule is obeyed, the minimum size rule requiring that a size of a do-not-inspect region is equal to or greater than a single pixel unit size while referring to the stored pixel unit size. A distance verification process includes calculating distances between pairs of do-not-inspect regions from among the do-not-inspect regions, and verifying whether a distance rule is obeyed, the distance rule requiring that the distance is in a range of greater than zero and less than a predetermined distance.
First claim
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The invention claimed is: 1. A method of inspecting a defect in a mask used in production of a circuit, the method comprising: executing by computer hardware implementing processes: calculating a width and a height of each of a plurality of rectangular shaped do-not-inspect regions of the mask based upon stored information specifying the do-not-inspect regions, and verifying whether a minimum size rule is obeyed, the minimum size rule requiring that the width and the height of a…
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Physics · mapped topic
- G03F1/84Primary
Physics · mapped topic
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- What does patent US9201296B2 cover?
- A verification method and apparatus for do-not-inspect region rules include storing information specifying do-not-inspect regions, and storing a pixel unit size which defines a length of a single pixel unit. A minimum size verification process includes calculating sizes of do-not-inspect regions, and verifying whether a minimum size rule is obeyed, the minimum size rule requiring that a size of…
- Who is the assignee on this patent?
- Kageyama Kiyoshi, Toppan Printing Co Ltd
- What technology area does this patent fall under?
- Primary CPC classification G03F1/84. Mapped technology areas include Physics.
- When was this patent published?
- Publication date Tue Dec 01 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).