Liquid crystal display and method of manufacturing the same

US9201265B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9201265-B2
Application numberUS-201414282310-A
CountryUS
Kind codeB2
Filing dateMay 20, 2014
Priority dateDec 18, 2013
Publication dateDec 1, 2015
Grant dateDec 1, 2015

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

An exemplary embodiment provides a liquid crystal display including: a substrate; a first wire grid polarizer; a thin film transistor; a pixel electrode; a roof layer; and a plurality of microcavities. The substrate has a bottom surface and a top surface. The first wire grid polarizer is disposed on the bottom surface of the substrate. The thin film transistor is disposed on the top surface of the substrate. The pixel electrode is connected to the thin film transistor. The roof layer is disposed to face the pixel electrode. The plurality of microcavities having injection holes are formed between the pixel electrode and the roof layer, the microcavities forming a liquid crystal layer containing liquid crystal molecules.

First claim

Opening claim text (preview).

What is claimed is: 1. A liquid crystal display comprising: a substrate having a bottom surface and a top surface; a first wire grid polarizer disposed on the bottom surface of the substrate; a thin film transistor disposed on the top surface of the substrate; a pixel electrode connected to the thin film transistor; a roof layer disposed to face the pixel electrode; and a plurality of microcavities having injection holes formed between the pixel electrode and the roof layer, the microcavities forming a liquid crystal layer containing liquid crystal molecules. 2. The liquid crystal display of claim 1 , further comprising a capping layer disposed on the roof layer, wherein the capping layer covers the injection holes. 3. The liquid crystal display of claim 2 , further comprising a second wire grid polarizer disposed on the capping layer. 4. The liquid crystal display of claim 3 , further comprising a passivation layer covering the second wire grid polarizer. 5. The liquid crystal display of claim 4 , wherein the passivation layer fills a groove of the second wire grid polarizer. 6. The liquid crystal display of claim 5 , further comprising a common electrode and a lower insulating layer disposed between the microcavities and the roof layer, wherein the lower insulating layer is disposed on the common electrode. 7. The liquid crystal display of claim 6 , wherein an injection hole formation region is formed between the microcavities, and the capping layer covers the injection hole formation region. 8. The liquid crystal display of claim 7 , wherein the thin film transistor is connected to a data line, and a partition wall formation portion is formed between the microcavities along an extension direction of the data line. 9. The liquid crystal display of claim 1 , further comprising a backlight unit configured to emit light disposed at a lower end of the first wire grid polarizer, wherein the light emitted from the backlight device passes toward the top surface of the substrate through the first wire grid polarizer. 10. The liquid crystal display of claim 1 , wherein the substrate is a flexible substrate. 11. A manufacturing method of a liquid crystal display, the method comprising: forming a thin film transistor on a top surface of a substrate; forming a pixel electrode to be connected to the thin film transistor; forming a sacrificial layer on the pixel electrode; forming a roof layer on the sacrificial layer; forming a plurality of microcavities having injection holes by removing the sacrificial layer; injecting a liquid crystal material into the microcavities; and forming a first wire grid polarizer on a bottom surface of the substrate. 12. The manufacturing method of claim 11 , further comprising forming a capping layer on the roof layer, wherein the capping layer is formed to cover the injection holes. 13. The manufacturing method of claim 12 , further comprising forming a second wire grid polarizer on a top surface of the capping layer. 14. The manufacturing method of claim 13 , further comprising forming a passivation layer on the capping layer to cover the second wire grid polarizer. 15. The manufacturing method of claim 14 , further comprising forming a common electrode and a lower insulating layer on the sacrificial layer, before the forming of the roof layer. 16. The manufacturing method of claim 15 , further comprising forming an injection hole formation region between the microcavities, wherein the capping layer is formed to cover the injection hole formation region. 17. The manufacturing method of claim 16 , wherein the injection hole formation region is formed to extend along a direction parallel with a gate line connected to the thin film transistor. 18. The manufacturing method of claim 17 , wherein the thin film transistor is connected to a data line, and a partition wall formation portion is formed between the microcavities along an extension direction of the data line. 19. The manufacturing method of claim 11 , wherein the substrate is formed as a flexible substrate.

Assignees

Inventors

Classifications

  • Polarisers · CPC title

  • Structures for producing distorted electric fields, e.g. bumps, protrusions, recesses, slits in pixel electrodes · CPC title

  • Filling or closing of cells · CPC title

  • characterised by their geometrical arrangement · CPC title

  • Reflective polarizers (G02F1/13362 takes precedence) · CPC title

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What does patent US9201265B2 cover?
An exemplary embodiment provides a liquid crystal display including: a substrate; a first wire grid polarizer; a thin film transistor; a pixel electrode; a roof layer; and a plurality of microcavities. The substrate has a bottom surface and a top surface. The first wire grid polarizer is disposed on the bottom surface of the substrate. The thin film transistor is disposed on the top surface of …
Who is the assignee on this patent?
Samsung Display Co Ltd
What technology area does this patent fall under?
Primary CPC classification G02F1/133528. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Dec 01 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).