Dimming method and circuit and controlled-silicon dimming circuit with the same

Patent metadata

Field	Value
Publication number	US-9198245-B2
Application number	US-201414504675-A
Country	US
Kind code	B2
Filing date	Oct 2, 2014
Priority date	Oct 15, 2013
Publication date	Nov 24, 2015
Grant date	Nov 24, 2015

Abstract

In one embodiment, a method of controlling dimming can include: (i) generating a dimming signal according to a DC input voltage signal; (ii) generating a voltage average value signal from the dimming signal; (iii) determining whether the dimming signal is in a positive half cycle or a negative half cycle; (iv) comparing the voltage average value signal against an output current feedback signal to generate a first comparison signal, and output a driving signal according to the first comparison signal when the dimming signal is in the positive half cycle; and (v) comparing the voltage average value signal against the output current feedback signal to generate a second comparison signal, and output the driving signal according to the second comparison signal when the dimming signal is in the negative half cycle.

First claim

What is claimed is:

1. A method of controlling dimming, the method comprising:
a) generating a dimming signal according to a DC input voltage signal;
b) generating a voltage average value signal from said dimming signal;
c) determining whether said dimming signal is in a positive half cycle or a negative half cycle;
d) comparing said voltage average value signal against an output current feedback signal to generate a first comparison signal, and generating a driving signal according to said first comparison signal when said dimming signal is in said positive half cycle; and
e) comparing said voltage average value signal against said output current feedback signal to generate a second comparison signal, and generating said driving signal according to said second comparison signal when said dimming signal is in said negative half cycle.

2. The method of claim 1 , wherein said determining whether said dimming signal is in said positive half cycle or said negative half cycle comprises determining an operation time duration of said dimming signal in each of said positive and negative half cycles.

3. The method of claim 1 , wherein said voltage average value signal is compared against said output current feedback signal in a present positive half cycle to output said first comparison signal when said dimming signal is in said positive half cycle.

4. The method of claim 1 , wherein said voltage average value signal is compared against said output current feedback signal in a present negative half cycle to output said second comparison signal when said dimming signal is in said negative half cycle.

5. The method of claim 1 , wherein said generating said driving signal according to said first comparison signal when said dimming signal is in said positive half cycle comprises comparing said first comparison signal against a ramp signal.

6. The method of claim 1 , wherein said generating said driving signal according to said second comparison signal when said dimming signal is in said negative half cycle comprises comparing said second comparison signal against a ramp signal.

7. A dimming control circuit, comprising:
a) a dimming signal generating circuit configured to generate a dimming signal according to a DC input voltage signal;
b) a voltage average value signal generating circuit configured to generate a voltage average value signal from said dimming signal;
c) a half cycle selection circuit configured to determine whether said dimming signal is in a positive half cycle or a negative half cycle, to compare said voltage average value signal against an output current feedback signal to generate a first comparison signal when said dimming signal is in said positive half cycle, and to compare said voltage average value signal against said output current feedback signal to generate a second comparison signal when said dimming signal is in said negative half cycle; and
d) a driving circuit configured to generate a driving signal according to said first comparison signal when said dimming signal is in said positive half cycle, and to generate said driving signal according to said second comparison signal when said dimming signal is in said negative half cycle.

8. The dimming control circuit of claim 7 , wherein said dimming signal generating circuit comprises:
a) a voltage dividing circuit coupled to a rectifier bridge, and being configured to sample said DC input voltage signal to generate an input voltage sense signal; and
b) a first comparator configured to receive a reference voltage signal, and said input voltage sense signal, and to generate said dimming signal.

9. The dimming control circuit of claim 8 , further comprising a silicon-controlled rectifier (SCR) coupled to said rectifier bridge.

10. The dimming control circuit of claim 7 , wherein said voltage average value signal generating circuit comprises a low pass filter circuit.

11. The dimming control circuit of claim 7 , wherein said half cycle selection circuit comprises:
a) first and second transconductance amplifying circuits configured to receive said voltage average value signal and said output current feedback signal;
b) first and second switches coupled between an output of said first transconductance amplifying circuit and said driving circuit;
c) a first capacitor coupled to ground and to a common node of said first and second switches;
d) third and fourth switches coupled between an output of said second transconductance amplifying circuit and said driving circuit;
e) a second capacitor coupled to ground and to a common node of said third and fourth switches; and
f) a flip-flop circuit having a clock input coupled to an output of said dimming signal generating circuit, an input coupled to a complementary output and to control terminals of said third and fourth switches, and an output coupled to control terminals of said first and second switches, wherein said first and second switches are on when said dimming signal is in said positive half cycle, and wherein said third and fourth switches are on when said dimming signal is in said negative half cycle.

12. The dimming control circuit of claim 11 , wherein said driving circuit comprises a second comparator having a first input terminal coupled to said second and fourth switches, a second input terminal coupled to a ramp signal, wherein said second comparator is configured to compare said first comparison signal against said ramp signal to generate said driving signal when said dimming signal is in said positive half cycle, and to compare said second comparison signal against said ramp signal to generate said driving signal when said dimming signal is in said negative half cycle.

13. The dimming control circuit of claim 7 , wherein said driving circuit is configured to compare said first comparison signal against a ramp signal to generate said driving signal when said dimming signal is in said positive half cycle, and to compare said second comparison signal against said ramp signal to generate said driving signal when said dimming signal is in said negative half cycle.

Assignees

• Silergy Semiconductor Technology Hangzhou Ltd

Inventors

• Deng Jian
• Huang Xiaodong

Classifications

• H05B45/10 Primary

  Controlling the intensity of the light · CPC title

• H05B33/0815 Primary

  Electricity · mapped topic

• H05B33/0845

  Electricity · mapped topic

• H05B45/14 Primary

  using electrical feedback from LEDs or from LED modules · CPC title

• H05B45/3725

  Switched mode power supply [SMPS] · CPC title