Non-volatile memory devices having dual heater configurations and methods of fabricating the same

Patent metadata

Field	Value
Publication number	US-9196827-B2
Application number	US-201213547663-A
Country	US
Kind code	B2
Filing date	Jul 12, 2012
Priority date	Nov 23, 2011
Publication date	Nov 24, 2015
Grant date	Nov 24, 2015

Abstract

A non-volatile memory device includes a data storage structure coupled between first and second conductive lines of the memory device. The data storage structure includes a conductive lower heater element, a data storage pattern, and a conductive upper heater element sequentially stacked. At least one sidewall surface of the data storage pattern is coplanar with a sidewall surface of the upper heater element thereabove and a sidewall surface of the lower heater element therebelow. Related fabrication methods are also discussed.

First claim

What is claimed is:

1. A non-volatile memory device comprising:
a data storage structure coupled between first and second conductive lines of the memory device, the data storage structure comprising a conductive lower heater element, a data storage pattern, and a conductive upper heater element sequentially stacked,
wherein the data storage pattern includes a sidewall surface that is coplanar with a sidewall surface of the upper heater element and a sidewall surface of the lower heater element,
wherein a surface of the lower heater element contacting the data storage pattern includes a protrusion along an edge thereof, and wherein a surface of the data storage pattern contacting the upper heater element includes a protrusion along an edge thereof.

2. The device of claim 1 , wherein a contact area between the upper heater element and the data storage pattern is substantially equal to a contact area between the lower heater element and the data storage pattern.

3. The device of claim 2 , further comprising:
a first insulating pattern including a planar surface that contacts the sidewall surfaces of the lower heater element, the data storage pattern, and the upper heater element.

4. The device of claim 3 , wherein the data storage pattern, the upper heater element, and the lower heater element include respective second sidewall surfaces opposite the respective first sidewall surfaces thereof, and wherein the second sidewall surface of the data storage pattern is coplanar with the second sidewall surface of the upper heater element and the second sidewall surface of the lower heater element.

5. The device of claim 4 , further comprising:
a second insulating pattern including a planar surface that contacts the second sidewall surfaces of the lower heater element, the data storage pattern, and the upper heater element, wherein the first and second insulating patterns define a trench therebetween including the data storage structure therein.

6. The device of claim 5 , wherein the data storage pattern, the upper heater element, and the lower heater element respectively include third and fourth opposing sidewall surfaces, wherein the third sidewall surfaces are coplanar, and wherein the fourth sidewall surfaces are coplanar.

7. The device of claim 1 , wherein at least one of the lower heater element or the upper heater element comprises a first portion including the sidewall surface thereof extending in a direction substantially perpendicular to a surface of an active region thereon, and a second portion extending in a direction substantially parallel to the surface of the active region.

8. The device of claim 1 , further comprising:
an upper conductive electrode between the upper heater element and the second conductive line,
wherein the upper conductive electrode has a lower electrical resistance than the upper heater element and a higher electrical resistance than the second conductive line.

9. The device of claim 5 , further comprising:
a diode element between the first conductive line and the lower heater element; and
a lower conductive pad between the diode element and the lower heater element,
wherein a contact area between the lower conductive pad and the lower heater element is not less than a contact area between the lower conductive pad and the diode element.

10. The device of claim 9 , wherein first and second opposing sidewall surfaces of the lower conductive pad are coplanar with sidewall surfaces of the first and second insulating patterns, respectively.

11. The device of claim 1 , wherein an upper surface and a sidewall surface of the upper heater element electrically contact the second conductive line.

12. A non-volatile memory device comprising:
a first conductive line on a substrate;
a switching element on the first conductive line;
a lower heater on the switching element;
a data storage pattern on the lower heater;
an upper heater on the data storage pattern; and
a second conductive line on the upper heater,
wherein a lateral surface of the upper heater is vertically aligned with a lateral surface of the lower heater and a lateral surface of the data storage pattern.

13. The device of claim 12 , wherein a contact surface between the upper heater and the data storage pattern has a substantially same area as a contact surface between the lower heater and the data storage pattern.

14. The device of claim 12 , wherein the lower heater, the data storage pattern, and the upper heater have a substantially same horizontal width.

15. The device of claim 12 , wherein an edge of a top surface of the lower heater protrudes upward, and wherein an edge of a top surface of the data storage pattern protrudes upward.

16. The device of claim 12 , further comprising a conductive pattern interposed between the switching element and the lower heater,
wherein the lower heater comprises:
an upper part having a vertical height greater than a horizontal width thereof; and
a lower part having a horizontal width greater than a vertical height thereof,
wherein the lower part of the lower heater is in contact with the conductive pattern.

17. A non-volatile memory device comprising:
a first conductive line disposed on a substrate;
a switching element disposed on the first conductive line;
a lower heater disposed on the switching element;
a data storage pattern disposed on the lower heater;
a high-resistance pattern disposed on the data storage pattern;
an intermediate resistance pattern disposed on the high-resistance pattern; and
a second conductive line formed on the intermediate resistance pattern and crossing the first conductive line,
wherein a lateral surface of the high-resistance pattern is vertically aligned with a lateral surface of the lower heater and a lateral surface of the data storage pattern,
wherein the high-resistance pattern includes a material having a higher electrical resistance than that of the second conductive line, and
wherein the intermediate resistance pattern includes a material having an electrical resistance higher than that of the second conductive line, and lower than that of the high-resistance pattern.

18. The device of claim 17 , wherein the high-resistance pattern includes titanium silicon nitride (TiSiN), the intermediate resistance pattern includes TiN, and the second conductive line includes copper (Cu).

19. The device of claim 17 , wherein the intermediate resistance pattern comprises:
an upper electrode in contact with the high-resistance pattern; and
a barrier metal pattern formed on the upper electrode and surrounding lateral and bottom surfaces of the second conductive line.

20. A non-volatile memory device comprising:
a data storage structure coupled between first and second conductive lines of the memory device, the data storage structure comprising a conductive lower heater element, a data storage pattern, and a conductive upper heater element sequentially stacked,
wherein the data storage pattern includes a sidewall surface that is coplanar with a sidewall surface of the upper heater element and a sidewall surface of the lower heater element, and wherein:
at least one of the lower heater element or the upper heater element comprises a first portion including the sidewall surface thereof extending in a direction substantially perpendicular to a surface of an active region thereon, and a second portion extending in a direction substantially parallel to the surface of the active region; or
the device further comprises an upper conductive

Assignees

• Oh Gyu-Hwan
• Park Doo-Hwan
• Kim Young-Kuk
• Samsung Electronics Co Ltd

Inventors

• Oh Gyu-Hwan
• Park Doo-Hwan
• Kim Young-Kuk

Classifications

• H10D89/931

  characterised by the dispositions of the protective arrangements · CPC title

• H01L27/2409

  Electricity · mapped topic

• H01L27/1021

  Electricity · mapped topic

• H05B3/141 Primary

  Conductive ceramics, e.g. metal oxides, metal carbides, barium titanate, ferrites, zirconia, vitrous compounds · CPC title

• H01L45/06

  Electricity · mapped topic