Pressure sensor device with gel retainer
US-9214402-B2 · Dec 15, 2015 · US
Backside bulk silicon MEMS
US9196752B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9196752-B2 |
| Application number | US-201113976086-A |
| Country | US |
| Kind code | B2 |
| Filing date | Dec 28, 2011 |
| Priority date | Dec 28, 2011 |
| Publication date | Nov 24, 2015 |
| Grant date | Nov 24, 2015 |
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- Title
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Abstract
Official abstract text for this publication.
An integrated circuit device that comprises a single semiconductor substrate, a device layer formed on a frontside of the single semiconductor substrate, a redistribution layer formed on a backside of the single semiconductor substrate, a through silicon via (TSV) formed within the single semiconductor substrate that is electrically coupled to the device layer and to the redistribution layer, a logic-memory interface (LMI) formed on a backside of the single semiconductor substrate that is electrically coupled to the redistribution layer, and a MEMS device formed on the backside of the single semiconductor substrate that is electrically coupled to the redistribution layer.
First claim
Opening claim text (preview).
What we claim is: 1. An apparatus comprising: a single semiconductor substrate having a frontside and a backside; a through-silicon via (TSV) formed within the semiconductor substrate that extends from the frontside of the substrate to the backside of the substrate; and a MEMS device at least partially within the substrate and on the backside of the substrate, the MEMS device electrically coupled to the TSV via a conductor, wherein the conductor is on the backside of the subst…
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Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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Frequently asked questions
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- What does patent US9196752B2 cover?
- An integrated circuit device that comprises a single semiconductor substrate, a device layer formed on a frontside of the single semiconductor substrate, a redistribution layer formed on a backside of the single semiconductor substrate, a through silicon via (TSV) formed within the single semiconductor substrate that is electrically coupled to the device layer and to the redistribution layer, a…
- Who is the assignee on this patent?
- Baskaran Rajashree, Pelto Christopher M, Intel Corp
- What technology area does this patent fall under?
- Primary CPC classification H01L29/84. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Nov 24 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).