Connection device, method for manufacturing connection structure, method for manufacturing stacked chip component and method for mounting electronic component

Patent metadata

Field	Value
Publication number	US-9196599-B2
Application number	US-201214355852-A
Country	US
Kind code	B2
Filing date	Oct 31, 2012
Priority date	Nov 7, 2011
Publication date	Nov 24, 2015
Grant date	Nov 24, 2015

Abstract

A connection device includes a mounting section on which an electronic component stacked with a thermosetting adhesive agent layer is mounted, a heat press head for heating and pressing the electronic component, a first elastic body that is disposed between the electronic component and a pressing surface of the heat press head so as to press an upper surface of the electronic component, and a support member that is disposed on a periphery of the electronic component and supports the first elastic body.

First claim

The invention claimed is:

1. A method for manufacturing a chip stacked component in which a plurality of chip substrates are stacked, each of the plurality of chip substrates is connected to one another electrically and mechanically, the method comprising:
mounting bumps formed on one surface of each chip substrate on an electrode formed on another surface of an adjacent chip substrate with a thermosetting adhesive agent interposed therebetween such that a chip stacked body on which a plurality of chip substrates are stacked is formed; and
disposing a first elastic body on an upper surface side of the chip stacked body, disposing a support member for supporting the first elastic body on a periphery of the chip stacked body, and heating and pressing the chip stacked body by using a heat press head with the first elastic body being interposed therebetween.

2. The method according to claim 1 , wherein the support member is a second elastic body having a hardness greater than a hardness of the first elastic body.

3. The method according to claim 2 , wherein each of the first elastic body and the second elastic body has a hardness that is between 20 and 60 when measured by a type-A durometer specified by JIS K 6253.

4. The method according to claim 3 , wherein the chip stacked body comprises at least one layer of a chip substrate having a thickness of 100 μm or less.

5. The method according to claim 1 , wherein a region on which the electronic component is mounted is divided into a plurality of regions by the support member such that a plurality of chip stacked components are simultaneously assembled thereon.

6. The method according to claim 1 , wherein the chip stacked body is mounted on a substrate or a wafer with a thermosetting adhesive agent being interposed therebetween and wherein the heating and pressing processes are carried out in a batch process.

Assignees

• Dexerials Corp

Inventors

• Saito Takayuki

Classifications

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/732

  between stacked chips · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title