Semiconductor bonding structure

Patent metadata

Field	Value
Publication number	US-9196595-B2
Application number	US-201414192029-A
Country	US
Kind code	B2
Filing date	Feb 27, 2014
Priority date	Feb 28, 2013
Publication date	Nov 24, 2015
Grant date	Nov 24, 2015

Abstract

The disclosure relates to a semiconductor bonding structure and process and a semiconductor chip. The semiconductor bonding structure includes a first pillar, a first interface, an intermediate area, a second interface and a second pillar in sequence. The first pillar, the second pillar and the intermediate area include a first metal. The first interface and the second interface include the first metal and an oxide of a second metal. The content percentage of the first metal in the first interface and the second interface is less than that of the first metal in the intermediate area.

First claim

What is claimed is:

1. A semiconductor bonding structure, comprising:
a first pillar comprising a first metal;
a second pillar comprising the first metal;
an intermediate area, located between the first pillar and the second pillar, and comprising the first metal;
a first interface, located between the first pillar and the intermediate area, and comprising the first metal and an oxide of a second metal, wherein the content percentage of the first metal in the first interface is less than that of the first metal in the intermediate area; and
a second interface, located between the second pillar and the intermediate area, and comprising the first metal and the oxide of the second metal, wherein the content percentage of the first metal in the second interface is less than that of the first metal in the intermediate area.

2. The semiconductor bonding structure according to claim 1 , wherein the first metal is different from the second metal, the first metal is selected from the group consisting of silver, gold, aluminum and copper, and the second metal is selected from the group consisting of silver, gold, platinum, palladium, osmium, iridium, ruthenium, titanium, magnesium, aluminum, copper, cobalt, nickel and zinc.

3. The semiconductor bonding structure according to claim 1 , wherein the first interface contacts the first pillar and the intermediate area, and the second interface contacts the second pillar and the intermediate area.

4. The semiconductor bonding structure according to claim 1 , wherein the first interface is a discontinuous interface so that the first pillar contacts the intermediate area, and the second interface is a discontinuous interface so that the second pillar contacts the intermediate area.

5. The semiconductor bonding structure according to claim 1 , wherein the first pillar and the second pillar are copper metal pillars.

6. The semiconductor bonding structure according to claim 1 , wherein the intermediate area, the first pillar and the second pillar do not include the oxide of the second metal.

7. The semiconductor bonding structure according to claim 1 , wherein the first metal in the intermediate area originates from the diffusion of the first metal in the first pillar and the second pillar.

8. A semiconductor bonding process, comprising:
(a) providing a first semiconductor element and a second semiconductor element, the first semiconductor element including at least one first pillar and at least one first diffusion layer, the first pillar comprising a first metal, the first diffusion layer being located at an end of the first pillar and comprising a second metal, the second semiconductor element including at least one second pillar and at least one second diffusion layer, the second pillar comprising the first metal, the second diffusion layer being located at an end of the second pillar and comprising the second metal, and the thickness of at least one of the first diffusion layer and the second diffusion layer being 1 nm to 30 nm;
(b) bonding the first semiconductor element to the second semiconductor element, so that the first diffusion layer contacts the second diffusion layer; and
(c) applying a bonding force to the first semiconductor element and the second semiconductor element for a period of time, so that the first metal of the first pillar is diffused towards the second pillar, the first metal of the second pillar is diffused towards the first pillar, and they contact to form an intermediate area; an oxide of the second metal of the first diffusion layer is diffused towards the first pillar and is mixed with the first metal to form a first interface; and the oxide of the second metal of the second diffusion layer is diffused towards the second pillar and is mixed with the first metal to form a second interface.

9. The semiconductor bonding process according to claim 8 , wherein in (a), the first semiconductor element includes a first semiconductor element body, an upper wiring layer, a lower wiring layer, a lower protection layer, an upper protection layer, at least one first UBM layer, the upper wiring layer and the lower wiring layer are respectively located on an upper surface and a lower surface of the first semiconductor element body, the lower protection layer covers the lower wiring layer and the lower surface of the first semiconductor element body, and has a plurality of openings to expose part of the lower wiring layer, the upper protection layer covers the upper wiring layer and the upper surface of the first semiconductor element body, and has a plurality of openings to expose part of the upper wiring layer, the first UBM layer is located at one of the openings of the upper protection layer, and contacts the upper wiring layer, the first pillar is located on the first UBM layer.

10. The semiconductor bonding process according to claim 8 , wherein in (a), the second semiconductor element includes a second semiconductor element body, a wiring layer, a protection layer, at least one second UBM layer, the wiring layer is located on a first surface of the second semiconductor element body, the protection layer covers the wiring layer and the first surface of the second semiconductor element body, and has a plurality of openings to expose part of the wiring layer, the second UBM layer is located at one of the openings of the protection layer, and contacts the wiring layer, the second pillar is located on the second UBM layer.

11. The semiconductor bonding process according to claim 8 , wherein in (c), a bonding temperature is further provided, wherein the bonding temperature is lower than 180° C.

12. The semiconductor bonding process according to claim 8 , wherein in (a), the first metal is different from the second metal, the first metal is selected from the group consisting of silver, gold, aluminum and copper, and the second metal is selected from the group consisting of silver, gold, platinum, palladium, osmium, iridium, ruthenium, titanium, magnesium, aluminum, copper, cobalt, nickel and zinc.

13. The semiconductor bonding process according to claim 8 , wherein in (c), the first interface contacts the first pillar and the intermediate area, and the second interface contacts the second pillar and the intermediate area.

14. The semiconductor bonding process according to claim 8 , wherein in (c), the first interface is a discontinuous interface so that the first pillar contacts the intermediate area, and the second interface is a discontinuous interface so that the second pillar contacts the intermediate area.

15. The semiconductor bonding process according to claim 8 , wherein in (c), the first pillar, the first diffusion layer, the second pillar and the second diffusion layer are heated at atmospheric pressure.

16. The semiconductor bonding process according to claim 8 , wherein in (c), the content percentage of the first metal in the first interface is less than that of the first metal in the intermediate area, and the content percentage of the first metal in the second interface is less than that of the first metal in the intermediate area.

17. The semiconductor bonding process according to claim 9 , wherein the first semiconductor element further includes a plurality of conductive vias, the conductive vias penetrate through the first semiconductor element body, and contact and are electrically connected to the upper wiring layer and the lower wiring layer.

Assignees

• Advanced Semiconductor Eng

Inventors

• Chen Kuo-Hua
• Lin Tzu-Hua
• Chen Kuan-Neng
• Huang Yan-Pin

Classifications

• H10W70/687

  characterized by the outer layers being for protection, e.g. solder masks, or for protection against chemical or mechanical damage · CPC title

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title

• H10W90/28

  the stacked chips having different sizes, e.g. chip stacks having a pyramidal shape · CPC title

• H10W72/07141

  Means for applying energy, e.g. ovens or lasers · CPC title

• H10W72/29

  Bond pads specially adapted therefor · CPC title