Array substrate and manufacturing method thereof
US-12185597-B2 · Dec 31, 2024 · US
US9196552B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9196552-B2 |
| Application number | US-201414539165-A |
| Country | US |
| Kind code | B2 |
| Filing date | Nov 12, 2014 |
| Priority date | Dec 2, 2013 |
| Publication date | Nov 24, 2015 |
| Grant date | Nov 24, 2015 |
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A display device is disclosed which includes: gate lines and data lines crossing each other to define unit pixel regions in a display area; a pixel electrode in each unit pixel region; a data shorting bar in a non-display area in substantially parallel with the gate lines; a gate shorting bar in the non-display area in substantially parallel with the data lines; gate link lines electrically connecting the gate lines to the gate shorting bar; data link lines electrically connecting the data lines to the data shorting bar; and shield electrodes on at least one of the gate link lines and the data link lines, the shield electrodes including a conductive material that has a higher melting temperature than that of the at least one of the gate link lines and the data link lines.
Opening claim text (preview).
What is claimed is: 1. A display device comprising: gate lines and data lines crossing each other to define unit pixel regions in a display area; a pixel electrode in each unit pixel region; a data shorting bar in a non-display area in substantially parallel with the gate lines; a gate shorting bar in the non-display area in substantially parallel with the data lines; gate link lines electrically connecting the gate lines to the gate shorting bar; data link lines electri…
Electricity · mapped topic
Electricity · mapped topic
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