Semiconductor memory apparatus and method for erasing the same

Patent metadata

Field	Value
Publication number	US-9196366-B2
Application number	US-201314029807-A
Country	US
Kind code	B2
Filing date	Sep 18, 2013
Priority date	Sep 18, 2013
Publication date	Nov 24, 2015
Grant date	Nov 24, 2015

Abstract

A flash memory with low power consumption and rapid operations is disclosed, including a memory array of memory cells, a word line selection circuit for selecting a row of cells, a current-type sensing circuit electrically connected with each bit line for sensing the current of a selected bit line, and an erase unit erasing the cells in a selected block of the array. The erase unit includes: an erase sequence that determines whether the current of each bit line in the erased block is larger than a first value and ends the erasure if the result is “yes”, and a soft-program sequence that performs a soft program verification, which applies a soft-program voltage to all word lines in the erased block and determines whether the current of each bit line is lower than a second value, and ends the soft programming if the result is “yes”.

First claim

What is claimed is:

1. A semiconductor memory apparatus, comprising:
a memory array, comprising a plurality of memory cells;
a word line selection circuit, configured to select a row of memory cells;
a current-type sensing circuit, electrically connected with respective bit lines of the memory array to sense a current of a selected bit line; and
an erase unit, configured to erase data of memory cells in a selected block of the memory array and comprising an erase sequence an…

Assignees

• Winbond Electronics Corp

Inventors

• Yano Masaru

Classifications

• G11C16/14 Primary

  Physics · mapped topic

• G11C16/26

  Physics · mapped topic

• G11C16/0483

  Physics · mapped topic

• G11C16/3409

  Physics · mapped topic