Noise suppression structure for differential pair
US-2024023227-A1 · Jan 18, 2024 · US
Printed wiring board, semiconductor package, and printed circuit board
US9192044B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9192044-B2 |
| Application number | US-201313862038-A |
| Country | US |
| Kind code | B2 |
| Filing date | Apr 12, 2013 |
| Priority date | Apr 23, 2012 |
| Publication date | Nov 17, 2015 |
| Grant date | Nov 17, 2015 |
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- Title
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Abstract
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First and second signal wiring patterns are formed in a first conductor layer. A first electrode pad electrically connected to the first signal wiring pattern through a first via and a second electrode pad electrically connected to the second signal wiring pattern through a second via are formed in a second conductor layer as a surface layer. A third conductor layer is disposed between the first conductor layer and the second conductor layer with an insulator interposed between those conductor layers. A first pad electrically connected to the first via is formed in the third conductor layer. The first pad includes an opposed portion which overlaps the second electrode pad as viewed in a direction perpendicular to the surface of a printed board and which is opposed to the second electrode pad through intermediation of the insulator. This enables reduction of crosstalk noise caused between the signal wirings.
First claim
Opening claim text (preview).
What is claimed is: 1. A printed wiring board having a plurality of conductor layers, the printed wiring board comprising: a first conductor layer having a first signal wiring pattern and a second signal wiring pattern formed therein; a second conductor layer which is formed on a second surface of the printed wiring board and which has a first external electrode pad and a second external electrode pad formed therein, the first external electrode pad being electrically connected…
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Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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Frequently asked questions
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- What does patent US9192044B2 cover?
- First and second signal wiring patterns are formed in a first conductor layer. A first electrode pad electrically connected to the first signal wiring pattern through a first via and a second electrode pad electrically connected to the second signal wiring pattern through a second via are formed in a second conductor layer as a surface layer. A third conductor layer is disposed between the firs…
- Who is the assignee on this patent?
- Canon Kk
- What technology area does this patent fall under?
- Primary CPC classification H05K1/0216. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Nov 17 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).