Local buried channel dielectric for vertical NAND performance enhancement and vertical scaling

Patent metadata

Field	Value
Publication number	US-9190490-B2
Application number	US-201313832721-A
Country	US
Kind code	B2
Filing date	Mar 15, 2013
Priority date	Mar 15, 2013
Publication date	Nov 17, 2015
Grant date	Nov 17, 2015

Abstract

A non-volatile memory device and a method for forming the non-volatile memory device are disclosed. The memory device utilizes a local buried channel dielectric in a NAND string that reduces bulk channel leakage at the edge of the NAND string where the electric field gradient along the direction of the string pillar is at or near a maximum during programming operations. The memory device comprises a channel that is coupled at one end to a bitline and at the other end to a source. A select gate is formed at the end of the channel coupled to the bitline to selectively control conduction between the bitline and the channel. At least one non-volatile memory cell is formed along the length of the channel between the select gate and the second end of the channel. A local dielectric region is formed within the channel at the first end of the channel.

First claim

The invention claimed is:

1. A memory device, comprising:
a channel comprising a first end, a second end and a length, the first end of the channel being coupled to a bitline and the second end of the channel being coupled to a source;
a select gate formed at the first end of the channel to selectively control conduction between the bitline and the channel;
at least one non-volatile memory cell formed along the length of the channel between the select gate and the second end o…

Assignees

• Intel Corp

Inventors

• Koval Randy J
• Simsek-Ege Fatma A

Classifications

• H10D30/693

  Electricity · mapped topic

• H10D30/689

  Electricity · mapped topic

• H10D30/025

  Electricity · mapped topic

• H10D30/63 Primary

  Electricity · mapped topic

• H01L29/7827

  Electricity · mapped topic