Method of fabricating integrated circuit transistors with multipart gate conductors

Patent metadata

Field	Value
Publication number	US-9190332-B1
Application number	US-201414185484-A
Country	US
Kind code	B1
Filing date	Feb 20, 2014
Priority date	Nov 26, 2008
Publication date	Nov 17, 2015
Grant date	Nov 17, 2015

Abstract

Metal-oxide-semiconductor transistors are provided. A metal-oxide-semiconductor transistor may be formed on a semiconductor substrate. Source and drain regions may be formed in the substrate. A gate insulator such as a high-K dielectric may be formed between the source and drain regions. A gate may be formed from multiple gate conductors. The gate conductors may be metals with different workfunctions. A first of the gate conductors may form a pair of edge gate conductors that are adjacent to dielectric spacers. An opening between the edge gate conductors may be filled with the second gate conductor to form a center gate conductor. A self-aligned gate formation process may be used in fabricating the metal-oxide-semiconductor transistor.

First claim

What is claimed is:

1. A method for fabricating a transistor comprising:
using a self-aligned gate formation process, depositing a first gate conductor on a gate insulator in the transistor during a first time period;
depositing a second gate conductor directly on top of the first gate conductor during a second time period that is different than the first time period; and forming first and second edge conductor portions on the gate insulator by simultaneously removing a portion…

Assignees

• Altera Corp

Inventors

• Liu Jun
• Ratnakumar Albert
• Xiang Qi
• Tung Jeffrey Xiaoqi

Classifications

• H10D64/01312

  Electricity · mapped topic

• H10D64/011

  Electricity · mapped topic

• H10D64/66

  Electricity · mapped topic

• H10D64/017

  Electricity · mapped topic

• H10D64/671 Primary

  Electricity · mapped topic