Integrated circuit comprising at least an integrated antenna

Patent metadata

Field	Value
Publication number	US-9188635-B2
Application number	US-201213560632-A
Country	US
Kind code	B2
Filing date	Jul 27, 2012
Priority date	Jul 28, 2011
Publication date	Nov 17, 2015
Grant date	Nov 17, 2015

Abstract

An integrated circuit on a substrate including at least one peripheral portion that surrounds an active area and is realized close to at least one scribe line providing separation with other integrated circuits realized on a same wafer. The integrated circuit includes at least one conductive structure that extends in its peripheral portion on different planes starting from the substrate and realizes an integrated antenna for the circuit.

First claim

What is claimed is:

1. An integrated circuit comprising:
a substrate including a peripheral portion that surrounds an active area supporting a transceiver circuit, wherein said peripheral portion is realized close to at least one scribe line, and
a conductive structure that extends above said peripheral portion on different planes starting from said substrate and comprising a plurality of first conductive lines realized in said different planes, each first conductive line forming a coil, with the coils made from the first conductive lines connected to form an integrated antenna having a first end and second end coupled to said transceiver circuit; and
another conductive structure that extends above said peripheral portion on different planes comprising a plurality of second conductive lines realized in said different planes to form a seal ring;
wherein the integrated antenna is positioned between the seal ring and the active area on the substrate.

2. Integrated circuit according to claim 1 , wherein the coils formed by said first conductive lines are arranged and electrically connected such that a length of said antenna develops in a vertical direction perpendicular to the substrate in the different planes starting from said substrate.

3. Integrated circuit according to claim 1 , wherein said seal ring comprises a plurality of pillar structures formed by the connection of second conductive lines belonging to different planes, said pillar structures being distributed in said peripheral portion.

4. Integrated circuit according to claim 3 , wherein said first conductive lines that form said antenna are serpentine-like shaped and surround at least partially said pillar structures of said seal ring.

5. Integrated circuit according to claim 3 , wherein said first conductive lines that form said antenna are chain-like shaped and completely surround said pillar structures, of said seal ring.

6. Integrated circuit according to claim 3 , further comprising reinforced pillar structures realized by portions of said second conductive lines and having greater sizes than corresponding sizes of said pillar structures of said seal ring, said reinforced pillar structures being placed in correspondence with mechanically stressed points of the integrated circuit.

7. Integrated circuit according to claim 1 , further comprising a junction suitably biased and realized in said substrate below said antenna.

8. Integrated circuit according to claim 1 , further comprising suitably doped areas realized in said substrate so as to extend substantially across said peripheral portion where said antenna is realized.

9. Integrated circuit according to claim 1 , further comprising at least one trench realized in said substrate so as to extend substantially across said peripheral portion where said antenna is realized and filled in with an insulating material.

10. Integrated circuit according to claim 3 , further comprising an opening for uncovering an upper portion of at least one of said pillar structures, which comprises a conductive line that extends up to said scribe line and/or at least one conductive line that extends up to said active area of said integrated circuit and realizes a pad for said integrated circuit and/or for structures realized in said scribe line.

11. Integrated circuit according to claim 3 , wherein said seal ring comprises at least one pillar structure provided with a conductive line realized above it and having greater sizes with respect to the second conductive lines that realize said pillar structure.

12. Integrated circuit according to claim 3 , further comprising at least one linear element that passes between said pillar structures of said seal ring and forms said antenna.

13. Integrated circuit according to claim 2 , wherein said first conductive lines, forming said coils of said antenna are interrupted in correspondence with a cutting area for realizing at least one pair of terminals of said antenna coupled to said transceiver circuit.

14. Integrated circuit according to claim 1 , further comprising a plurality of third conductive lines connected so as to form a further seal ring in said peripheral portion of said integrated circuit and positioned between said antenna and said scribe line.

15. Integrated circuit according to claim 1 , wherein said first conductive lines that form said antenna are shaped so as to overhang at least in part said second conductive lines that form said seal ring.

16. Integrated circuit according to claim 1 , further comprising a trench structure realized in a central portion of said scribe line.

17. Integrated circuit according to claim 16 , wherein said trench structure penetrates in said scribe line up to at least the level of said substrate.

18. Integrated circuit according to claim 16 , wherein said trench structure penetrates in said scribe line and at least partially in said substrate.

19. Integrated circuit according to claim 16 , wherein said trench structure is covered by a protective layer.

20. Integrated circuit according to claim 1 , wherein said antenna acts also as seal ring of said integrated circuit.

21. Integrated circuit according to claim 1 , wherein said conductive structure comprises at least one trench structure suitably coated by at least one layer of conductive material to form a coil of said antenna.

22. Integrated circuit according to claim 21 , wherein said trench structure is filled in at least partially with a nonconductive filling material.

23. Integrated circuit according to claim 22 , wherein said trench structure comprises above said nonconductive filling material at least one further conductive material to form a further coil of said antenna.

24. Integrated circuit according to claim 21 , wherein said antenna is formed inside said trench structure by means of a plurality of layers of conductive material arranged at different levels with respect to said substrate and separated by a nonconductive material.

25. Integrated circuit according to claim 21 , wherein said antenna also acts as seal ring of said integrated circuit.

26. Integrated circuit according to claim 1 , wherein said antenna comprises support structures arranged between its conductive paths.

27. Integrated circuit according to claim 1 , wherein said antenna and/or said seal ring comprises at least one material having magnetic features.

28. Integrated circuit according to claim 1 , further comprising, adjacent to said antenna at least one trench comprising in turn at least one material having magnetic features for realizing a magnetic trench.

29. Integrated circuit according to claim 28 , further comprising at least one pair of magnetic trenches realized on the opposite part with respect to said antenna.

30. Integrated circuit according to claim 29 , further comprising a further insulating trench realized in said substrate below said antenna and below said magnetic trenches.

31. Integrated circuit according to claim 30 , further comprising insulating and/or magnetic trenches, inside or around said further insulating trench.

32. Testing system of at least one integrated circuit provided with an antenna and realized according to claim 1 , said testing system comprising at least one probe card provided with a probe head wherein said probe card comprises at least one tes

Assignees

• Pagani Alberto
• Finocchiaro Alessandro
• St Microelectronics Srl

Inventors

• Pagani Alberto
• Finocchiaro Alessandro

Classifications

• H10P74/277

  Circuits for electrically characterising or monitoring manufacturing processes, e.g. circuits in tested chips or circuits in testing wafers · CPC title

• H10P74/273

  Interconnections for measuring or testing, e.g. probe pads · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W72/5363

  the connected ends being wedge-shaped · CPC title