Memory performance evaluation using address mapping information
US-2024394164-A1 · Nov 28, 2024 · US
Storage control apparatus and storage control method
US9183136B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9183136-B2 |
| Application number | US-201213512143-A |
| Country | US |
| Kind code | B2 |
| Filing date | May 16, 2012 |
| Priority date | May 16, 2012 |
| Publication date | Nov 10, 2015 |
| Grant date | Nov 10, 2015 |
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Abstract
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A storage control apparatus comprises a storage unit, an association unit, and an execution unit. The storage unit stores association information showing multiple physical chunks which are configured in a physical address space of a nonvolatile semiconductor memory, multiple logical storage areas which are configured in a logical address space of the nonvolatile semiconductor memory, multiple logical chunks which are respectively associated with the multiple physical chunks, and an association between a logical storage area and a logical chunk. The association unit changes the association by changing the association information in accordance with a state of the nonvolatile semiconductor memory, and identifies based on the association information a physical storage area corresponding to a logical storage area specified in an input/output request from a computer. The execution unit executes the input/output request with respect to the identified physical storage area.
First claim
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The invention claimed is: 1. A storage control apparatus, comprising: a storage unit configured to store association information showing multiple physical chunks which are configured in a physical address space of a nonvolatile semiconductor memory, multiple logical storage areas which are configured in a logical address space of the nonvolatile semiconductor memory, multiple logical chunks which are respectively associated with the multiple physical chunks, and an association be…
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- G06F12/0246Primary
Physics · mapped topic
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- What does patent US9183136B2 cover?
- A storage control apparatus comprises a storage unit, an association unit, and an execution unit. The storage unit stores association information showing multiple physical chunks which are configured in a physical address space of a nonvolatile semiconductor memory, multiple logical storage areas which are configured in a logical address space of the nonvolatile semiconductor memory, multiple l…
- Who is the assignee on this patent?
- Kawamura Atsushi, Ogawa Junji, Hitachi Ltd
- What technology area does this patent fall under?
- Primary CPC classification G06F12/0246. Mapped technology areas include Physics.
- When was this patent published?
- Publication date Tue Nov 10 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).