Semiconductor nanowire thermoelectric materials and devices, and processes for producing same

Patent metadata

Field	Value
Publication number	US-9181092-B2
Application number	US-201313945171-A
Country	US
Kind code	B2
Filing date	Jul 18, 2013
Priority date	May 7, 2007
Publication date	Nov 10, 2015
Grant date	Nov 10, 2015

Abstract

The present invention provides nanowires and nanoribbons that are well suited for use in thermoelectric applications. The nanowires and nanoribbons are characterized by a periodic compositional longitudinal modulation. The nanowires are constructed using lithographic techniques from thin semiconductor membranes, or “nanomembranes.”

First claim

What is claimed is:

1. A method of making at least one nanowire comprising a plurality of quantum dots along its length, the method comprising forming a first set of strips comprising a first semiconductor material separated by lateral channels, growing a second semiconductor material in the lateral channels to provide a nanomembrane comprising alternating strips of the first and second semiconductor materials, and cutting at least one nanowire out of the nanomembrane, wherein the longitudinal axis of the at least one nanowire is not aligned with the longitudinal axes of the strips of first and second semiconductor materials, the at least one nanowire comprising quantum dots comprising the first and second semiconductor materials along its length.

2. The method of claim 1 , wherein the longitudinal axis of the at least one nanowire is perpendicular to, or substantially perpendicular to, the longitudinal axes of the strips of first and second semiconductor materials.

3. The method of claim 1 , wherein the first semiconductor material is Si and the second semiconductor material is a SiGe alloy.

4. The method of claim 1 , wherein the first semiconductor material is Si(001).

5. The method of claim 4 , wherein the at least one nanowire is are oriented along the <011> direction of the Si.

6. The method of claim 4 , wherein the at least one nanowire is are oriented along the <110> direction of the Si.

7. The method of claim 4 , wherein the at least one nanowire is are oriented along the <001> direction of the Si.

8. The method of claim 1 , wherein the first semiconductor material is Si(110).

9. The method of claim 1 , wherein the first semiconductor material is Si(111).

10. The method of claim 1 , wherein the crystallographic orientation of the semiconductor materials are orientations that cannot be grown using vapor-liquid-solid growth.

11. The method of claim 1 , further comprising growing a third semiconductor material in the lateral channels to provide a nanomembrane comprising alternating strips of the first, second and third semiconductor materials, wherein the at least one nanowire comprises quantum dots comprising the first, second and third semiconductor materials along its length.

12. The method of claim 1 , wherein thousands of nanowires are cut out of the nanomembrane.

13. The method of claim 1 , wherein millions of nanowires are cut out of the nanomembrane.

14. The method of claim 1 , wherein the first and second semiconductor materials comprise alloys of the same material, but have different compositional ratios.

15. The method of claim 1 , wherein the nanomembrane comprising alternating strips of the first and second semiconductor material is formed on a layer of sacrificial material.

16. The method of claim 15 further comprising releasing the at least one nanowire from the layer of sacrificial material.

17. The method of claim 15 , wherein the first semiconductor material comprises the device layer of a semiconductor-on-insulator substrate and the layer of sacrificial material is a buried oxide layer of the semiconductor-on-insulator substrate.

18. The method of claim 17 , wherein the first semiconductor material comprises the silicon device layer of a silicon-on-insulator substrate.

19. The method of claim 17 , wherein the first semiconductor material comprises the germanium device layer of a germanium-on-insulator substrate.

20. The method of claim 17 , wherein the first semiconductor material comprises the strained semiconductor device layer of a strained-semiconductor-on-insulator substrate.

Assignees

• Wisconsin Alumni Res Found

Inventors

• Lagally Max G
• Evans Paul G
• Ritz Clark S

Classifications

• H10D62/814

  Quantum box structures · CPC title

• H10D62/118 Primary

  Nanostructure semiconductor bodies · CPC title

• H10D62/121 Primary

  oriented parallel to substrates · CPC title

• H01L29/127

  Electricity · mapped topic

• H01L35/34

  Electricity · mapped topic