Systems and methods for characterizing loops based on single-ended line testing (SELT)

US9178990B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9178990-B2
Application numberUS-16448808-A
CountryUS
Kind codeB2
Filing dateJun 30, 2008
Priority dateJun 30, 2008
Publication dateNov 3, 2015
Grant dateNov 3, 2015

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Abstract

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Systems and methods for characterizing loops based on frequency domain reflectometry single-ended line testing (FDR-SELT) are described. One embodiment includes a method for determining whether a straight-loop departure condition exists on a loop under test. First, an un-calibrated echo signal is received. A region associated with the loop under test, a platform type, and estimated the length of the loop under test are then used together with the received un-calibrated echo signal to determine whether the loop is not a straight loop is determined through determining whether at least one differentiating feature is present in the received signal. Another embodiment includes a method for determining a loop gauge for a loop under test through analyzing characteristics relating to local maxima and local minima of the received un-calibrated echo signal using the region, platform type, and the estimated loop length.

First claim

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At least the following is claimed: 1. A method for determining whether a straight-loop departure condition exists on a loop under test, the loop connecting a customer premise equipment (CPE) modem to the central office (CO) modern in a communication system, comprising: receiving, at the CO modem or CPE modern, an un-calibrated echo signal for the loop under test using frequency domain reflectometry single-ended line testing (FDR-SELT), a geographical region associated with the loo…

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What does patent US9178990B2 cover?
Systems and methods for characterizing loops based on frequency domain reflectometry single-ended line testing (FDR-SELT) are described. One embodiment includes a method for determining whether a straight-loop departure condition exists on a loop under test. First, an un-calibrated echo signal is received. A region associated with the loop under test, a platform type, and estimated the length o…
Who is the assignee on this patent?
Dinesh Vaibhav, Raheja Kunal, Duvaut Patrick, and 1 more
What technology area does this patent fall under?
Primary CPC classification H04M3/306. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Nov 03 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).