Low-power high-performance clock path architecture
US-2024393824-A1 · Nov 28, 2024 · US
N factorial dual data rate clock and data recovery
US9178690B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9178690-B2 |
| Application number | US-201414252450-A |
| Country | US |
| Kind code | B2 |
| Filing date | Apr 14, 2014 |
| Priority date | Oct 3, 2013 |
| Publication date | Nov 3, 2015 |
| Grant date | Nov 3, 2015 |
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- Title
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Abstract
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System, methods and apparatus are described that facilitate transmission of data over a multi-wire data communications link, particularly between two devices within an electronic apparatus. Each symbol in a sequence of symbols received from a plurality of signal wires is received in an odd transmission interval or an even transmission interval. A first clock signal is generated from transitions in signaling state of the wires occurring between each odd transmission interval and a consecutive even transmission interval. A second clock signal is generated from transitions in signaling state of the plurality of wires occurring between each even transmission interval and a consecutive odd transmission interval. The first and second clock signals are used to capture symbols received in even and odd transmission intervals, respectively.
First claim
Opening claim text (preview).
What is claimed is: 1. A method of data communications, comprising: receiving a sequence of symbols from a plurality of signal wires, wherein each symbol in the sequence of symbols is received during one of an odd transmission interval or an even transmission interval; generating a first clock signal from transitions in signaling state of the plurality of signal wires occurring between each odd transmission interval and a consecutive even transmission interval; generating a s…
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Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
- H04L7/0337Primary
Electricity · mapped topic
Electricity · mapped topic
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- What does patent US9178690B2 cover?
- System, methods and apparatus are described that facilitate transmission of data over a multi-wire data communications link, particularly between two devices within an electronic apparatus. Each symbol in a sequence of symbols received from a plurality of signal wires is received in an odd transmission interval or an even transmission interval. A first clock signal is generated from transitions…
- Who is the assignee on this patent?
- Qualcomm Inc
- What technology area does this patent fall under?
- Primary CPC classification H04L7/0337. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Nov 03 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).