Receiver with clock recovery circuit and adaptive sample and equalizer timing

Patent metadata

Field	Value
Publication number	US-9178688-B2
Application number	US-201314014047-A
Country	US
Kind code	B2
Filing date	Aug 29, 2013
Priority date	Jan 9, 2007
Publication date	Nov 3, 2015
Grant date	Nov 3, 2015

Abstract

A receiver is equipped with an adaptive phase-offset controller and associated timing-calibration circuitry that together shift the timing for a data sampler and a digital equalizer. The sample and equalizer timing is shifted to a position with less residual inter-symbol interference (ISI) energy relative to the current symbol. The shifted position may be calculated using a measure of signal quality, such as a receiver bit-error rate or a comparison of filter-tap values, to optimize the timing of data recovery.

First claim

What is claimed is:

1. A receiver comprising:
an equalizer to receive a data signal and issue an equalized signal;
a reference sampler to sample the data signal before the equalizer to produce reference samples;
clock recovery circuitry to recover a reference clock signal from the reference samples;
an adaptive phase-offset controller to receive the recovered reference clock signal and produce a data clock signal phase adjusted with respect to the recovered reference clock s…

Assignees

• Rambus Inc

Inventors

• Lin Qi
• Leibowitz Brian
• Lee Hae-Chang
• Ren Jihong
• Oh Kyung Suk
• Zerbe Jared L

Classifications

• H04L43/028

  Electricity · mapped topic

• H04L7/0087

  Electricity · mapped topic

• H04L2025/03617

  Electricity · mapped topic

• H04L25/03254 Primary

  Electricity · mapped topic

• H04L25/03057

  Electricity · mapped topic