Integration circuit
US-2015349753-A1 · Dec 3, 2015 · US
US9178496B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9178496-B2 |
| Application number | US-201514605805-A |
| Country | US |
| Kind code | B2 |
| Filing date | Jan 26, 2015 |
| Priority date | Mar 6, 2013 |
| Publication date | Nov 3, 2015 |
| Grant date | Nov 3, 2015 |
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A particular method includes receiving a retention signal. In response to receiving the retention signal, the method includes retaining state information in a non-volatile stage of a retention register and reducing power to a volatile stage of the retention register. The non-volatile stage may be powered by an external voltage source. The volatile stage may be powered by an internal voltage source.
Opening claim text (preview).
What is claimed is: 1. A circuit comprising: a first retention register that includes a first non-volatile region and a first volatile region; and a second retention register that includes a second non-volatile region and a second volatile region, wherein the first retention register is coupled to the second retention register, and the second volatile region comprises: a multiplexer configured to select a shift data signal from the first retention register or an input data sign…
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