Semiconductor device
US-2024413252-A1 · Dec 12, 2024 · US
Thin film transistor display panel and manufacturing method thereof
US9178024B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9178024-B2 |
| Application number | US-201213464613-A |
| Country | US |
| Kind code | B2 |
| Filing date | May 4, 2012 |
| Priority date | Dec 12, 2011 |
| Publication date | Nov 3, 2015 |
| Grant date | Nov 3, 2015 |
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Abstract
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A method for manufacturing a thin film transistor array panel includes forming a gate line and a gate electrode protruding from the gate line on a substrate; forming a gate insulating layer on the gate line and the gate electrode; depositing sequentially a semiconductor material and a metal material on the gate insulating layer; performing a first etching operation on the semiconductor material and the metal material using a first mask to form a semiconductor layer and a metal layer, the metal layer including a data line, a source electrode, and a drain electrode, in which the drain electrode protrudes from the data line, and the source electrode and the drain electrode having an integral shape; and performing a second etching operation on the metal layer using a second mask to divide the source electrode and the drain electrode.
First claim
Opening claim text (preview).
What is claimed is: 1. A method for manufacturing a thin film transistor array panel, comprising: forming a gate line and a gate electrode protruding from the gate line on a substrate; forming a gate insulating layer on the gate line and the gate electrode; depositing a semiconductor material on the gate insulating layer; depositing a metal material directly on the semiconductor material; performing a first etching operation on the semiconductor material and the metal mate…
Assignees
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Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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Frequently asked questions
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- What does patent US9178024B2 cover?
- A method for manufacturing a thin film transistor array panel includes forming a gate line and a gate electrode protruding from the gate line on a substrate; forming a gate insulating layer on the gate line and the gate electrode; depositing sequentially a semiconductor material and a metal material on the gate insulating layer; performing a first etching operation on the semiconductor material…
- Who is the assignee on this patent?
- Kim Ki-Won, Yoon Kap Soo, Lee Woo Geun, and 5 more
- What technology area does this patent fall under?
- Primary CPC classification H10D30/6729. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Nov 03 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).